Issued Patents All Time
Showing 25 most recent of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9455186 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-09-27 |
| 9431535 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Haining Yang | 2016-08-30 |
| 9406560 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-08-02 |
| 9385038 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-07-05 |
| 9276111 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Haining Yang | 2016-03-01 |
| 9171848 | Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer scheme | Herbert L. Ho, Jin Ping Liu | 2015-10-27 |
| 9157980 | Measuring metal line spacing in semiconductor devices | Stephen E. Greco | 2015-10-13 |
| 9076847 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2015-07-07 |
| 9059177 | Doping of copper wiring structures in back end of line processing | Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-Tsu Tseng | 2015-06-16 |
| 9018097 | Semiconductor device processing with reduced wiring puddle formation | Hanako Henry, Tze-man Ko, Yiheng Xu, Shaoning Yao | 2015-04-28 |
| 8896069 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Haining Yang | 2014-11-25 |
| 8889504 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Haining Yang | 2014-11-18 |
| 8853746 | CMOS devices with stressed channel regions, and methods for fabricating the same | Xiangdong Chen, Kenneth T. Settlemyer, Jr., Haining Yang | 2014-10-07 |
| 8765602 | Doping of copper wiring structures in back end of line processing | Daniel C. Edelstein, Tze-man Ko, Andrew H. Simon, Wei-Tsu Tseng | 2014-07-01 |
| 8697528 | Method of forming a planar field effect transistor structure with recesses for epitaxially deposited source/drain regions | — | 2014-04-15 |
| 8685806 | Silicon-on-insulator substrate with built-in substrate junction | Junedong Lee, Dominic J. Schepis | 2014-04-01 |
| 8623673 | Structure and method for detecting defects in BEOL processing | Tze-man Ko, Yiheng Xu, Shaoning Yao | 2014-01-07 |
| 8482009 | Silicon-on-insulator substrate with built-in substrate junction | Junedong Lee, Dominic J. Schepis | 2013-07-09 |
| 8377785 | Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure | — | 2013-02-19 |
| 8362531 | Method of patterning semiconductor structure and structure thereof | James J. Toomey | 2013-01-29 |
| 8293631 | Semiconductor devices having tensile and/or compressive stress and methods of manufacturing | Haining Yang | 2012-10-23 |
| 8198194 | Methods of forming p-channel field effect transistors having SiGe source/drain regions | Jong-ho Yang, Hyung-Rae Lee, Jin-Ping Han, Chung Woh Lai, Henry K. Utomo | 2012-06-12 |
| 8159031 | SOI substrates and SOI devices, and methods for forming the same | Zhijiong Luo, Haining Yang | 2012-04-17 |
| 8110464 | SOI protection for buried plate implant and DT bottle ETCH | Herbert L. Ho, Ravi M. Todi | 2012-02-07 |
| 8063449 | Semiconductor devices and methods of manufacture thereof | Jin-Ping Han, Henry K. Utomo, Rajendran Krishnasamy | 2011-11-22 |