Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7718993 | Pattern enhancement by crystallographic etching | Kenneth T. Settlemyer, Jr., James J. Toomey, Haining Yang | 2010-05-18 |
| 7667255 | Deep trench inter-well isolation structure | — | 2010-02-23 |
| 7666721 | SOI substrates and SOI devices, and methods for forming the same | Zhijiong Luo, Haining Yang | 2010-02-23 |
| 7652336 | Semiconductor devices and methods of manufacture thereof | Jin-Ping Han, Henry K. Utomo, Rajendran Krishnasamy | 2010-01-26 |
| 7635899 | Structure and method to form improved isolation in a semiconductor device | Haining Yang, William C. Wille | 2009-12-22 |
| 7598572 | Silicided polysilicon spacer for enhanced contact area | Sunfei Fang, Ja-Hum Ku, Yong Meng Lee | 2009-10-06 |
| 7598540 | High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same | Bruce B. Doris, David R. Medeiros, Anna W. Topol | 2009-10-06 |
| 7585773 | Non-conformal stress liner for enhanced MOSFET performance | Sunfei Fang, Jun Jung Kim | 2009-09-08 |
| 7582516 | CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy | Sunfei Fang, Judson R. Holt | 2009-09-01 |
| 7569489 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Haining Yang | 2009-08-04 |
| 7569446 | Semiconductor structure and method of manufacture | Bruce B. Doris, Haining Yang | 2009-08-04 |
| 7566949 | High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching | Haining Yang | 2009-07-28 |
| 7560382 | Embedded interconnects, and methods for forming same | Haining Yang | 2009-07-14 |
| 7550330 | Deep junction SOI MOSFET with enhanced edge body contacts | Zhijiong Luo, Jack A. Mandelman | 2009-06-23 |
| 7528451 | CMOS gate conductor having cross-diffusion barrier | Huilong Zhu, Haining Yang | 2009-05-05 |
| 7518191 | Silicon on insulator devices having body-tied-to-source and methods of making | Jack A. Mandelman, Keith Kwong Hon Wong, Chih-Chao Yang, Haining Yang | 2009-04-14 |
| 7517767 | Forming conductive stud for semiconductive devices | Sunfei Fang, Jiang Yan | 2009-04-14 |
| 7504309 | Pre-silicide spacer removal | Sunfei Fang, Jiang Yan, Jun Jung Kim, Yaocheng Liu, Huilong Zhu | 2009-03-17 |
| 7504299 | Folded node trench capacitor | Carl Radens | 2009-03-17 |
| 7488660 | Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure | Sunfei Fang | 2009-02-10 |
| 7488659 | Structure and methods for stress concentrating spacer | — | 2009-02-10 |
| 7485520 | Method of manufacturing a body-contacted finfet | Huilong Zhu, Jack A. Mandelman, Werner Rausch | 2009-02-03 |
| 7485516 | Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation | Jinhong Li, Zhijiong Luo | 2009-02-03 |
| 7485508 | Two-sided semiconductor-on-insulator structures and methods of manufacturing the same | Haining Yang | 2009-02-03 |
| 7482215 | Self-aligned dual segment liner and method of manufacturing the same | Sunfei Fang, Jiang Yan | 2009-01-27 |