Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10651179 | Integrated circuit device and method of manufacturing the same | Hong-Bae Park, Myeong-Cheol Kim, Jin-Wook Lee, Sung-Kee Han | 2020-05-12 |
| 10134856 | Semiconductor device including contact plug and method of manufacturing the same | Da-Il Eom, Jeong-Ik Kim, Chul-Sung Kim, Jun Ki Park, Sang-Jin Hyun | 2018-11-20 |
| 10014304 | Integrated circuit device and method of manufacturing the same | Hong-Bae Park, Myeong-Cheol Kim, Jin-Wook Lee, Sung-Kee Han | 2018-07-03 |
| 9613002 | Method of calibrating target values and processing systems configured to calibrate the target values | Chang-Ho Han, Dae Wook Kim, Jin Young Lee, Sung Won Choi, Byoung Hoon Kim +2 more | 2017-04-04 |
| 9508727 | Integrated circuit device and method of manufacturing the same | Hong-Bae Park, Myeong-Cheol Kim, Jin-Wook Lee, Sung-Kee Han | 2016-11-29 |
| 8016941 | Method and apparatus for manufacturing a semiconductor | Matthias Hierlemann | 2011-09-13 |
| 8008177 | Method for fabricating semiconductor device using a nickel salicide process | Min-chul San, Chul-Sung Kim, Kwan-Jong Roh, Min-Joo Kim | 2011-08-30 |
| 7911001 | Methods for forming self-aligned dual stress liners for CMOS semiconductor devices | Kyoung-Woo Lee, Taehoon Lee, Seung-Man Choi, Thomas W. Dyer | 2011-03-22 |
| 7816271 | Methods for forming contacts for dual stress liner CMOS semiconductor devices | Kyoung-Woo Lee, Wanjae Park, Chong-Kwang Chang, Theodorus E. Standaert | 2010-10-19 |
| 7800134 | CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein | Kyoung-Woo Lee, Jae-eon Park | 2010-09-21 |
| 7790622 | Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes | Kyoung-Woo Lee, Jun Jung Kim, Chong-Kwang Chang, Min-Chul Sun, Jong-ho Yang +1 more | 2010-09-07 |
| 7781276 | Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities | Kyoung-Woo Lee, Seung-Man Choi | 2010-08-24 |
| 7781322 | Nickel alloy salicide transistor structure and method for manufacturing same | Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim | 2010-08-24 |
| 7772643 | Methods of fabricating semiconductor device having a metal gate pattern | Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim | 2010-08-10 |
| 7615432 | HDP/PECVD methods of fabricating stress nitride structures for field effect transistors | Junjung Kim, Jae-Eun Park, Daewon Yang | 2009-11-10 |
| 7598572 | Silicided polysilicon spacer for enhanced contact area | Thomas W. Dyer, Sunfei Fang, Yong Meng Lee | 2009-10-06 |
| 7586175 | Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface | Kyoung-Woo Lee, Ki-Chul Park, Seung-Man Choi | 2009-09-08 |
| 7576407 | Devices and methods for constructing electrically programmable integrated fuses for low power applications | Young-Gun Ko, Minchul Sun, Robert Weiser | 2009-08-18 |
| 7544996 | Methods of fabricating a semiconductor device having a metal gate pattern | Chang-Won Lee, Seong-Jun Heo, Sun-Pil Youn, Sung-Man Kim | 2009-06-09 |
| 7541288 | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques | Jun Jung Kim, Jae-eon Park, Sunfei Fang, Alois Gutmann, O-Sung Kwon +2 more | 2009-06-02 |
| 7534678 | Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby | Kyoung-Woo Lee, Jae-eon Park | 2009-05-19 |
| 7514354 | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | Ki-Chul Park, Seung-Man Choi | 2009-04-07 |
| 7501651 | Test structure of semiconductor device | Min-Chul Sun, Brian J. Greene, Manfred Eller, Roman Knoefler, Zhijiong Luo | 2009-03-10 |
| 7465617 | Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer | Chang-Won Lee, Seong-Jun Heo, Min-Chul Sun, Sun-Pil Youn | 2008-12-16 |
| 7435673 | Methods of forming integrated circuit devices having metal interconnect structures therein | Kyoung-Woo Lee, Duk-Ho Hong, Wan Jae Park | 2008-10-14 |