Issued Patents All Time
Showing 25 most recent of 309 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12376369 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2025-07-29 |
| 12277960 | Modified top electrode contact for MRAM embedding in advanced logic nodes | Ashim Dutta, Dominik Metzler, Oscar van der Straten | 2025-04-15 |
| 12033892 | Structure and method to improve FAV RIE process margin and electromigration | Benjamin D. Briggs, Joe Lee | 2024-07-09 |
| 11955152 | Dielectric fill for tight pitch MRAM pillar array | Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein | 2024-04-09 |
| 11937514 | High-density memory devices using oxide gap fill | Daniel C. Edelstein, Chih-Chao Yang | 2024-03-19 |
| 11869783 | Optimizating semiconductor binning by feed-forward process adjustment | Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Michael Rizzolo, James H. Stathis | 2024-01-09 |
| 11837501 | Selective recessing to form a fully aligned via | Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee | 2023-12-05 |
| 11812668 | Pillar-based memory hardmask smoothing and stress reduction | Michael Rizzolo, Ashim Dutta, Dominik Metzler | 2023-11-07 |
| 11710658 | Structure and method to improve FAV RIE process margin and Electromigration | Benjamin D. Briggs, Joe Lee | 2023-07-25 |
| 11664271 | Dual damascene with short liner | Koichi Motoyama, Oscar van der Straten, Joseph F. Maniscalco, Alexander Reznicek, Raghuveer R. Patlolla | 2023-05-30 |
| 11615988 | FinFET devices | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2023-03-28 |
| 11600325 | Non volatile resistive memory logic device | Hsueh-Chung Chen, Mary Claire Silvestre, Soon-Cheon Seo, Chi-Chun Liu, Fee Li Lie +2 more | 2023-03-07 |
| 11569442 | Dielectric retention and method of forming memory pillar | Saba Zare, Michael Rizzolo, Mona A. Ebrish | 2023-01-31 |
| 11502242 | Embedded memory devices | Ashim Dutta, Chih-Chao Yang, Michael Rizzolo | 2022-11-15 |
| 11462583 | Embedding magneto-resistive random-access memory devices between metal levels | Ashim Dutta, Chih-Chao Yang, Daniel C. Edelstein, John C. Arnold | 2022-10-04 |
| 11302630 | Electrode-via structure | Chih-Chao Yang, Daniel C. Edelstein | 2022-04-12 |
| 11257717 | Selective recessing to form a fully aligned via | Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee | 2022-02-22 |
| 11244907 | Metal surface preparation for increased alignment contrast | Tianji Zhou, Saumya Sharma, Dominik Metzler, Chih-Chao Yang | 2022-02-08 |
| 11239278 | Bottom conductive structure with a limited top contact area | Chih-Chao Yang, Baozhen Li, Koichi Motoyama | 2022-02-01 |
| 11239421 | Embedded BEOL memory device with top electrode pillar | Dexin Kong, Soon-Cheon Seo, Shyng-Tsong Chen, Youngseok Kim | 2022-02-01 |
| 11223008 | Pillar-based memory hardmask smoothing and stress reduction | Michael Rizzolo, Ashim Dutta, Dominik Metzler | 2022-01-11 |
| 11217742 | Bottom electrode for semiconductor memory device | Chih-Chao Yang, Daniel C. Edelstein | 2022-01-04 |
| 11189693 | Transistor having reduced contact resistance | Veeraraghavan S. Basker, Kangguo Cheng, Junli Wang | 2021-11-30 |
| 11177437 | Alignment through topography on intermediate component for memory device patterning | Hao Tang, Michael Rizzolo, Injo Ok | 2021-11-16 |
| 11164779 | Bamboo tall via interconnect structures | Chih-Chao Yang, Michael Rizzolo | 2021-11-02 |