Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
KC

Kangguo Cheng — 2,819 Patents

IBM: 2575 patents #1 of 70,183Top 1%
Globalfoundries: 269 patents #3 of 4,424Top 1%
TETessera: 34 patents #14 of 271Top 6%
SSStmicroelectronics Sa: 19 patents #244 of 1,676Top 15%
ASAdeia Semiconductor Solutions: 13 patents #1 of 57Top 2%
ETElpis Technologies: 12 patents #1 of 121Top 1%
CEA: 6 patents #716 of 7,956Top 9%
Samsung: 5 patents #22,775 of 75,807Top 35%
GUGlobalfoundries U.S.: 5 patents #117 of 665Top 20%
RERenesas Electronics: 4 patents #1,016 of 4,529Top 25%
IBInternational Business: 1 patents #4 of 119Top 4%
Schenectady, NY: #1 of 1,353 inventorsTop 1%
New York: #1 of 115,490 inventorsTop 1%
Overall (All Time): #6 of 4,157,543Top 1%
2819 Patents All Time
Kangguo Cheng has been granted 2,819 US patents while listed as an inventor at IBM. The first was granted in 2004 and the most recent in September 2025. Kangguo Cheng ranks #6 of 4,157,543 US inventors in our database (top 0.00%). Patent records list Kangguo Cheng in Schenectady, NY, US.

Patents per Year

Patents granted per year, 2004 to 2025Bar chart with a peak of 370 patents in 2017.peak 3702004: 1 patents20042005: 6 patents2006: 8 patents2007: 11 patents20072008: 23 patents2009: 28 patents2010: 44 patents20102011: 38 patents2012: 46 patents2013: 97 patents20132014: 130 patents2015: 181 patents2016: 280 patents20162017: 370 patents2018: 338 patents2019: 354 patents20192020: 332 patents2021: 270 patents2022: 70 patents20222023: 74 patents2024: 59 patents2025: 59 patents2025

Issued Patents All Time

Showing 1–25 of 2,819 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12432968 Nanowire source/drain formation for nanosheet device Ruilong Xie, Julien Frougier, Alexander Reznicek 2025-09-30
12431469 Vertically stacked FET with strained channel Shogo Mochizuki, Juntao Li 2025-09-30
12426338 Buried power rail with robust connection to a wrap around contact Ruilong Xie, Julien Frougier, Chanro Park 2025-09-23
12426314 Strain generation and anchoring in gate-all-around field effect transistors Julien Frougier, Sung-Dae Suk, Andrew M. Greene, Ruilong Xie 2025-09-23
12419080 Semiconductor structure with wrapped-around backside contact Ruilong Xie, Chanro Park, Min Gyu Sung, Julien Frougier 2025-09-16
12414352 Two-dimensional vertical fins 2025-09-09
12407532 Gain cell memory based physically unclonable function 2025-09-02
12402545 Stacked cross-point phase change memory Carl Radens, Ruilong Xie, Juntao Li 2025-08-26
12402403 Air gap spacer for metal gates Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan 2025-08-26
12396247 Work function metal patterning for nanosheet CFETs Ruilong Xie, Chen Zhang, Juntao Li 2025-08-19
12396225 Method to release nano sheet after nano sheet fin recess Chanro Park, Ruilong Xie, Juntao Li, Choonghyun Lee 2025-08-19
12389813 Resistive switching memory cell Julien Frougier, Ruilong Xie, Chanro Park 2025-08-12
12389609 Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers Julien Frougier, Ruilong Xie, Heng Wu, Min Gyu Sung, Chanro Park 2025-08-12
12382665 Increased gate length at given footprint for nanosheet device Ruilong Xie, Julien Frougier, Chanro Park 2025-08-05
12382708 Vertical stacked nanosheet CMOS transistors with different work function metals Juntao Li, Ruilong Xie, Chanro Park 2025-08-05
12382719 Power gating dummy power transistors for back side power delivery networks Tao Li, Ruilong Xie 2025-08-05
12382662 Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors Julien Frougier, Ruilong Xie, Chanro Park, Andrew Gaul 2025-08-05
12376369 FinFET devices Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang 2025-07-29
12376503 Phase change material including deuterium Juntao Li, Arthur Roy Gasasira, LOUIS ZUOGUANG LIU, Amlan Majumdar 2025-07-29
12369367 Bulk nanosheet with dielectric isolation Bruce B. Doris, Junli Wang 2025-07-22
12369379 Nanosheet transistor Juntao Li, Heng Wu, Peng Xu 2025-07-22
12363977 Forming dielectric sidewall and bottom dielectric isolation in Fork-FET devices Julien Frougier, Ruilong Xie, Dimitri Houssameddine 2025-07-15
12356680 Nanosheet device with air-gaped source/drain regions Huimei Zhou, Yi Song, Ruilong Xie 2025-07-08
12349457 Stacked transistors having bottom contact with replacement spacer Ruilong Xie, Julien Frougier, Heng Wu 2025-07-01
12342738 Resistive memory for analog computing 2025-06-24