Issued Patents All Time
Showing 25 most recent of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12376503 | Phase change material including deuterium | Kangguo Cheng, Juntao Li, Arthur Roy Gasasira, LOUIS ZUOGUANG LIU | 2025-07-29 |
| 11978799 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2024-05-07 |
| 10978562 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2021-04-13 |
| 10937907 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2021-03-02 |
| 10937871 | III-V transistor device with self-aligned doped bottom barrier | Cheng-Wei Cheng, Pranita Kerber, Yanning Sun | 2021-03-02 |
| 10559666 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2020-02-11 |
| 10367093 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2019-07-30 |
| 10366892 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2019-07-30 |
| 10249719 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2019-04-02 |
| 10243050 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2019-03-26 |
| 10141437 | Extreme high mobility CMOS logic | Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Justin K. Brask +3 more | 2018-11-27 |
| 10014377 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2018-07-03 |
| 9985113 | Fabrication process for mitigating external resistance of a multigate device | Anirban Basu, Guy M. Cohen | 2018-05-29 |
| 9941363 | III-V transistor device with self-aligned doped bottom barrier | Cheng-Wei Cheng, Pranita Kerber, Yanning Sun | 2018-04-10 |
| 9922830 | Hybrid III-V technology to support multiple supply voltages and off state currents on same chip | Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight | 2018-03-20 |
| 9882021 | Planar III-V field effect transistor (FET) on dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu +1 more | 2018-01-30 |
| 9865688 | Device isolation using preferential oxidation of the bulk substrate | Anirban Basu, Guy M. Cohen, Yu Zhu | 2018-01-09 |
| 9806195 | Method for fabricating transistor with thinned channel | Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle +3 more | 2017-10-31 |
| 9773903 | Asymmetric III-V MOSFET on silicon substrate | Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Renee T. Mo, Yanning Sun | 2017-09-26 |
| 9761724 | Semiconductor device structures and methods of forming semiconductor structures | Justin K. Brask, Jack T. Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta +1 more | 2017-09-12 |
| 9748357 | III-V MOSFET with strained channel and semi-insulating bottom barrier | Anirban Basu, Guy M. Cohen | 2017-08-29 |
| 9711648 | Structure and method for CMP-free III-V isolation | Effendi Leobandung, Chung-Hsun Lin, Yanning Sun | 2017-07-18 |
| 9704958 | III-V field effect transistor on a dielectric layer | Cheng-Wei Cheng, Edward W. Kiewra, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun | 2017-07-11 |
| 9691856 | Extreme high mobility CMOS logic | Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Justin K. Brask +3 more | 2017-06-27 |
| 9666684 | III-V semiconductor device having self-aligned contacts | Anirban Basu, Yanning Sun | 2017-05-30 |