Issued Patents All Time
Showing 25 most recent of 625 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433007 | Transistor gate trench engineering to decrease capacitance and resistance | Seung Hoon Sung, Willy Rachmady, Han Wui Then, Marko Radosavljevic | 2025-09-30 |
| 12426247 | Capacitor connections in dielectric layers | Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang +13 more | 2025-09-23 |
| 12414339 | Formation of gate spacers for strained PMOS gate-all-around transistor structures | Ashish Agrawal, Gilbert Dewey, Siddharth Chouksey, Cheng-Ying Huang | 2025-09-09 |
| 12376362 | Field effect transistors with a gated oxide semiconductor source/drain spacer | Gilbert Dewey, Rafael Rios, Van H. Le | 2025-07-29 |
| 12349416 | Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures | Gilbert Dewey, Abhishek A. Sharma, Van H. Le, Shriram Shivaraman, Seung Hoon Sung +4 more | 2025-07-01 |
| 12342614 | Asymmetric gate structures and contacts for stacked transistors | Cheng-Ying Huang, Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady +2 more | 2025-06-24 |
| 12310101 | Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication | Ashish Verma Penumatcha, Seung Hoon Sung, Uygar E. Avci, Tristan A. Tronic, Shriram Shivaraman +5 more | 2025-05-20 |
| 12288803 | Transistor with isolation below source and drain | Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma +3 more | 2025-04-29 |
| 12266570 | Self-aligned interconnect structures and methods of fabrication | Kimin Jun, Souvik Ghosh, Willy Rachmady, Ashish Agrawal, Siddharth Chouksey +5 more | 2025-04-01 |
| 12255234 | Integrated circuit structures having germanium-based channels | Siddharth Chouksey, Glenn A. Glass, Anand S. Murthy, Harold W. Kennel, Tahir Ghani +2 more | 2025-03-18 |
| 12243875 | Forksheet transistors with dielectric or conductive spine | Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose +4 more | 2025-03-04 |
| 12238913 | Two transistor memory cell using stacked thin-film transistors | Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-Hua Wang +5 more | 2025-02-25 |
| 12224202 | Forming an oxide volume within a fin | Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2025-02-11 |
| 12199142 | Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions | Siddharth Chouksey, Stephen M. Cea, Ashish Agrawal, Willy Rachmady | 2025-01-14 |
| 12191395 | Dual gate control for trench shaped thin film transistors | Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Shriram Shivaraman, Benjamin Chu-Kung +2 more | 2025-01-07 |
| 12191349 | Reducing off-state leakage in semiconductor devices | Dipanjan Basu, Cory E. Weber, Justin R. Weber, Sean T. Ma, Harold W. Kennel +3 more | 2025-01-07 |
| 12183831 | Self-aligned contacts for thin film transistors | Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Gilbert Dewey, Ravi Pillarisetty +4 more | 2024-12-31 |
| 12176284 | Through plate interconnect for a vertical MIM capacitor | Travis W. Lajoie, Abhishek A. Sharma, Juan G. Alzate-Vinasco, Chieh-Jen Ku, Shem Ogadhoh +6 more | 2024-12-24 |
| 12142689 | Transistor including wrap around source and drain contacts | Sean T. Ma, Abhishek A. Sharma, Gilbert Dewey, Van H. Le | 2024-11-12 |
| 12125917 | Thin film transistors having double gates | Abhishek A. Sharma, Van H. Le, Tahir Ghani, Gilbert Dewey | 2024-10-22 |
| 12119387 | Low resistance approaches for fabricating contacts and the resulting structures | Gilbert Dewey, Nazila Haratipour, Siddharth Chouksey, Jitendra Kumar Jha, Matthew V. Metz +6 more | 2024-10-15 |
| 12119409 | Multi-layer crystalline back gated thin film transistor | Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Shriram Shivaraman +6 more | 2024-10-15 |
| 12120865 | Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure | Cheng-Ying Huang, Ashish Agrawal, Gilbert Dewey, Abhishek A. Sharma, Wilfred Gomes | 2024-10-15 |
| 12087750 | Stacked-substrate FPGA semiconductor devices | Abhishek A. Sharma, Willy Rachmady, Ravi Pillarisetty, Gilbert Dewey | 2024-09-10 |
| 12080643 | Integrated circuit structures having differentiated interconnect lines in a same dielectric layer | Travis W. Lajoie, Abhishek A. Sharma, Juan G. Alzate Vinasco, Chieh-Jen Ku, Shem Ogadhoh +6 more | 2024-09-03 |