Issued Patents All Time
Showing 1–25 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12376353 | Source/drain regions in integrated circuit structures | Sean T. Ma, Andy Wei | 2025-07-29 |
| 12328936 | Gate spacing in integrated circuit structures | Andy Wei, Sean T. Ma | 2025-06-10 |
| 12315805 | Self-aligned lateral contacts | Andy Wei, Yang-Chun Cheng, Shaestagir Chowdhury | 2025-05-27 |
| 12237388 | Transistor arrangements with stacked trench contacts and gate straps | Andy Wei, Changyok Park, Hyuk-Ju Ryu, Charles H. Wallace, Mohit K. HARAN | 2025-02-25 |
| 12211898 | Device contact sizing in integrated circuit structures | Andy Wei, Sean T. Ma | 2025-01-28 |
| 12211786 | Stacked vias with bottom portions formed using selective growth | Andy Wei | 2025-01-28 |
| 12148751 | Use of a placeholder for backside contact formation for transistor arrangements | Andy Wei, Anand S. Murthy, Mauro J. Kobrinsky | 2024-11-19 |
| 12142516 | Self aligned buried power rail | Nicholas V. LiCausi, Lars Liebmann | 2024-11-12 |
| 12094822 | Buried power rails with self-aligned vias to trench contacts | Andy Wei, Changyok Park | 2024-09-17 |
| 11984487 | Non-planar transistor arrangements with asymmetric gate enclosures | Sean T. Ma | 2024-05-14 |
| 11973121 | Device contacts in integrated circuit structures | Andy Wei, Mwilwa Tambwe, Sean T. Ma, Piyush Mohan Sinha | 2024-04-30 |
| 11916106 | Source/drain regions in integrated circuit structures | Sean T. Ma, Andy Wei | 2024-02-27 |
| 11916010 | Back end of line integration for self-aligned vias | Andy Wei | 2024-02-27 |
| 11749715 | Isolation regions in integrated circuit structures | Sean T. Ma, Andy Wei | 2023-09-05 |
| 11482524 | Gate spacing in integrated circuit structures | Andy Wei, Sean T. Ma | 2022-10-25 |
| 11450736 | Source/drain regions in integrated circuit structures | Sean T. Ma, Andy Wei | 2022-09-20 |
| 11430866 | Device contact sizing in integrated circuit structures | Andy Wei, Sean T. Ma | 2022-08-30 |
| 11342409 | Isolation regions in integrated circuit structures | Sean T. Ma, Andy Wei | 2022-05-24 |
| 11309210 | Self aligned buried power rail | Nicholas V. LiCausi, Lars Liebmann | 2022-04-19 |
| 11264463 | Multiple fin finFET with low-resistance gate structure | Andy Wei | 2022-03-01 |
| 11127627 | Method for forming an interconnection structure | Frederic Lazzarino, Juergen Boemmels | 2021-09-21 |
| 11061315 | Hybrid optical and EUV lithography | Jia Zeng, Lei Sun, Geng Han | 2021-07-13 |
| 10833161 | Semiconductor device and method | Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels | 2020-11-10 |
| 10770388 | Transistor with recessed cross couple for gate contact over active region integration | Ruilong Xie, Veeraraghavan S. Basker, Kangguo Cheng, Jia Zeng, Youngtag Woo +1 more | 2020-09-08 |
| 10700170 | Multiple fin finFET with low-resistance gate structure | Andy Wei | 2020-06-30 |