Issued Patents All Time
Showing 51–75 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10043703 | Apparatus and method for forming interconnection lines having variable pitch and variable widths | Nicholas V. LiCausi | 2018-08-07 |
| 10026824 | Air-gap gate sidewall spacer and method | Daniel Chanemougame, Andre P. Labonte, Ruilong Xie, Lars Liebmann, Nigel G. Cave | 2018-07-17 |
| 10014390 | Inner spacer formation for nanosheet field-effect transistors with tall suspensions | Julien Frougier, Ruilong Xie | 2018-07-03 |
| 10002786 | Interconnection cells having variable width metal lines and fully-self aligned variable length continuity cuts | Nicholas V. LiCausi | 2018-06-19 |
| 9960256 | Merged gate and source/drain contacts in a semiconductor device | Andy Wei | 2018-05-01 |
| 9905473 | Self-aligned contact etch for fabricating a FinFET | Vimal Kamineni, Michael V. Aquilino | 2018-02-27 |
| 9899268 | Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device | Andy Wei | 2018-02-20 |
| 9887127 | Interconnection lines having variable widths and partially self-aligned continuity cuts | Nicholas V. LiCausi | 2018-02-06 |
| 9852984 | Cut first alternative for 2D self-aligned via | Andy Wei, Sudharshanan Raghunathan | 2017-12-26 |
| 9852986 | Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit | Jason E. Stephens | 2017-12-26 |
| 9825031 | Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices | Andy Wei, Jason E. Stephens, David Permana, Jagannathan Vasudevan | 2017-11-21 |
| 9818876 | Method for fabricating a finFET metallization architecture using a self-aligned contact etch | — | 2017-11-14 |
| 9818651 | Methods, apparatus and system for a passthrough-based architecture | Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason E. Stephens +3 more | 2017-11-14 |
| 9818640 | Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines | Jason E. Stephens | 2017-11-14 |
| 9818623 | Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit | Jason E. Stephens, Byoung Youp Kim, Craig Child | 2017-11-14 |
| 9818641 | Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines | Jason E. Stephens | 2017-11-14 |
| 9812400 | Contact line having insulating spacer therein and method of forming same | Veeraraghavan S. Basker, Keith H. Tabakman, Patrick Carpenter, Michael V. Aquilino | 2017-11-07 |
| 9812396 | Interconnect structure for semiconductor devices with multiple power rails and redundancy | Jason E. Stephens, Shreesh Narasimha, Patrick R. Justison, Byoung Youp Kim, Craig Child | 2017-11-07 |
| 9812351 | Interconnection cells having variable width metal lines and fully-self aligned continuity cuts | Nicholas V. LiCausi, Lars Liebmann | 2017-11-07 |
| 9812324 | Methods to control fin tip placement | Lei Zhuang, Lars Liebmann, Stuart A. Sieg, Fee Li Lie, Mahender Kumar +3 more | 2017-11-07 |
| 9805988 | Method of forming semiconductor structure including suspended semiconductor layer and resulting structure | Steven Bentley | 2017-10-31 |
| 9793169 | Methods for forming mask layers using a flowable carbon-containing silicon dioxide material | Huy Cao, Huang Liu, Songkram Srivathanakul | 2017-10-17 |
| 9786545 | Method of forming ANA regions in an integrated circuit | Jason E. Stephens, Byoung Youp Kim, Craig Child, Shreesh Narasimha | 2017-10-10 |
| 9779943 | Compensating for lithographic limitations in fabricating semiconductor interconnect structures | Jason E. Stephens | 2017-10-03 |
| 9691775 | Combined SADP fins for semiconductor devices and methods of making the same | Nicholas V. LiCausi, Eric S. Kozarsky | 2017-06-27 |