Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AW

Andy Wei — 213 Patents

Globalfoundries: 132 patents #8 of 4,424Top 1%
AMD: 61 patents #93 of 9,280Top 2%
Intel: 20 patents #2,048 of 30,777Top 7%
Yamhill, OR: #1 of 29 inventorsTop 4%
Oregon: #50 of 28,073 inventorsTop 1%
Overall (All Time): #2,931 of 4,157,543Top 1%
213 Patents All Time
Andy Wei has been granted 213 US patents while listed as an inventor at Globalfoundries. The first was granted in 2003 and the most recent in September 2025. Andy Wei ranks #2,931 of 4,157,543 US inventors in our database (top 0.07%). Patent records list Andy Wei in Yamhill, OR, US.

Issued Patents All Time

Showing 1–25 of 213 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12426307 Dual metal gate structures on nanoribbon semiconductor devices Yang-Chun Cheng, Dax M. Crum 2025-09-23
12376353 Source/drain regions in integrated circuit structures Sean T. Ma, Guillaume Bouche 2025-07-29
12327791 Integrated circuit structures with gate cuts above buried power rails 2025-06-10
12328936 Gate spacing in integrated circuit structures Guillaume Bouche, Sean T. Ma 2025-06-10
12315805 Self-aligned lateral contacts Yang-Chun Cheng, Shaestagir Chowdhury, Guillaume Bouche 2025-05-27
12237388 Transistor arrangements with stacked trench contacts and gate straps Changyok Park, Guillaume Bouche, Hyuk-Ju Ryu, Charles H. Wallace, Mohit K. HARAN 2025-02-25
12211898 Device contact sizing in integrated circuit structures Guillaume Bouche, Sean T. Ma 2025-01-28
12211786 Stacked vias with bottom portions formed using selective growth Guillaume Bouche 2025-01-28
12199161 Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication Charles H. Wallace, Mohit K. HARAN 2025-01-14
12148751 Use of a placeholder for backside contact formation for transistor arrangements Anand S. Murthy, Mauro J. Kobrinsky, Guillaume Bouche 2024-11-19 $25,575,000
12094822 Buried power rails with self-aligned vias to trench contacts Guillaume Bouche, Changyok Park 2024-09-17 $19,251,000
11973121 Device contacts in integrated circuit structures Guillaume Bouche, Mwilwa Tambwe, Sean T. Ma, Piyush Mohan Sinha 2024-04-30 $26,151,000
11916010 Back end of line integration for self-aligned vias Guillaume Bouche 2024-02-27 $28,450,000
11916106 Source/drain regions in integrated circuit structures Sean T. Ma, Guillaume Bouche 2024-02-27 $28,450,000
11749715 Isolation regions in integrated circuit structures Guillaume Bouche, Sean T. Ma 2023-09-05 $19,899,000
11508847 Transistor arrangements with metal gate cuts and recessed power rails Sean T. Ma, Piyush Mohan Sinha 2022-11-22 $12,862,000
11482524 Gate spacing in integrated circuit structures Guillaume Bouche, Sean T. Ma 2022-10-25 $11,792,000
11450736 Source/drain regions in integrated circuit structures Sean T. Ma, Guillaume Bouche 2022-09-20 $15,654,000
11430866 Device contact sizing in integrated circuit structures Guillaume Bouche, Sean T. Ma 2022-08-30 $13,077,000
11342409 Isolation regions in integrated circuit structures Guillaume Bouche, Sean T. Ma 2022-05-24 $18,289,000
11264463 Multiple fin finFET with low-resistance gate structure Guillaume Bouche 2022-03-01 $213,052,000
10700170 Multiple fin finFET with low-resistance gate structure Guillaume Bouche 2020-06-30 $39,055,000
10644136 Merged gate and source/drain contacts in a semiconductor device Guillaume Bouche 2020-05-05 $25,055,000
10396026 Precut metal lines Guillaume Bouche, Mark A. Zaleski 2019-08-27 $31,250,000
10262941 Devices and methods for forming cross coupled contacts Guillaume Bouche, Jason E. Stephens, Tuhin Guha Neogi, Kai Sun, Deniz E. Civay +1 more 2019-04-16 $37,439,000