Issued Patents All Time
Showing 1–25 of 174 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10644152 | Buried-channel low noise transistors and methods of making such devices | Alban Zaka, Luca Pirro, Tom Herrmann, El Mehdi Bazizi | 2020-05-05 |
| 10580863 | Transistor element with reduced lateral electrical field | Damien Angot, Alban Zaka, Tom Herrmann, Venkata Naga Ranjith Kuma Nelluri, Lars Mueller-Meskamp +1 more | 2020-03-03 |
| 10340380 | Three-dimensional transistor with improved channel mobility | Stefan Flachowsky, Ralf Richter, Peter Javorka | 2019-07-02 |
| 10283490 | Communicating optical signals between stacked dies | Sven Beyer, Alexander Ebermann | 2019-05-07 |
| 10157996 | Methods for forming integrated circuits that include a dummy gate structure | Elliot John Smith, Nigel Chan, Sven Beyer | 2018-12-18 |
| 10056376 | Ferroelectric FinFET | Stefan Flachowsky, Ralf Illgen | 2018-08-21 |
| 9960184 | FDSOI-capacitor | Peter Baars, Hans-Peter Moll | 2018-05-01 |
| 9917087 | Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same | Stefan Flachowksy, Juergen Faul | 2018-03-13 |
| 9881841 | Methods for fabricating integrated circuits with improved implantation processes | Alban Zaka, Ran Yan, El Mehdi Bazizi | 2018-01-30 |
| 9806067 | Die-die stacking | Sven Beyer, Alexander Ebermann | 2017-10-31 |
| 9793372 | Integrated circuit including a dummy gate structure and method for the formation thereof | Elliot John Smith, Nigel Chan, Sven Beyer | 2017-10-17 |
| 9735174 | FDSOI—capacitor | Peter Baars, Hans-Peter Moll | 2017-08-15 |
| 9698179 | Capacitor structure and method of forming a capacitor structure | Elliot John Smith, Sven Beyer, Alexander Ebermann | 2017-07-04 |
| 9620589 | Integrated circuits and methods of fabrication thereof | Nicolas Sassiat, Ran Yan, Kun-Hsien Lin | 2017-04-11 |
| 9608112 | BULEX contacts in advanced FDSOI techniques | Elliot John Smith, Sven Beyer, Tom Hasche | 2017-03-28 |
| 9608003 | Integrated circuit product with bulk and SOI semiconductor devices | Peter Baars, Hans-Peter Moll | 2017-03-28 |
| 9590118 | Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure | Elliot John Smith, Sven Beyer, Nigel Chan | 2017-03-07 |
| 9583240 | Temperature independent resistor | Stefan Flachowsky, Ralf Illgen | 2017-02-28 |
| 9553046 | E-fuse in SOI configuration | Peter Baars, Hans-Peter Moll | 2017-01-24 |
| 9502564 | Fully depleted device with buried insulating layer in channel region | Hans-Peter Moll, Peter Baars | 2016-11-22 |
| 9490344 | Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process | Stefan Flachowsky, Thilo Scheiper | 2016-11-08 |
| 9490189 | Semiconductor device comprising a stacked die configuration including an integrated peltier element | Uwe Griebenow, Thilo Scheiper, Sven Beyer | 2016-11-08 |
| 9472642 | Method of forming a semiconductor device structure and such a semiconductor device structure | Stefan Flachowsky, Ralf Richter, Peter Javorka | 2016-10-18 |
| 9466717 | Complex semiconductor devices of the SOI type | Ran Yan, Alban Zaka | 2016-10-11 |
| 9461145 | OPC enlarged dummy electrode to eliminate ski slope at eSiGe | Ran Yan, Martin Gerhardt | 2016-10-04 |