Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12013493 | Lidar system including light emitter for multiple receiving units | Jürgen Brugger, Heiko Leppin, Jan Michael Masur | 2024-06-18 |
| 11947038 | Wavelength adaptive narrow band optical filter for a LIDAR system | Heiko Leppin | 2024-04-02 |
| 11745453 | Method of making and using a reusable mold for fabrication of optical elements | Jacob A. Bergam | 2023-09-05 |
| 11579265 | Lidar system with crosstalk reduction comprising a power supply circuit layer stacked between an avalanche-type diode layer and a read-out circuit layer | — | 2023-02-14 |
| 11031406 | Semiconductor devices having silicon/germanium active regions with different germanium concentrations | Gunter Grasshoff, Carsten Peters | 2021-06-08 |
| 10923579 | Semiconductor device with interconnect to source/drain | Hans-Juergen Thees, Peter Baars | 2021-02-16 |
| 10811433 | High-voltage transistor device with thick gate insulation layers | Nigel Chan, Nilesh Kenkare | 2020-10-20 |
| 10707330 | Semiconductor device with interconnect to source/drain | Hans-Juergen Thees, Peter Baars | 2020-07-07 |
| 10593674 | Deep fence isolation for logic cells | Ming-Cheng Chang, Nigel Chan | 2020-03-17 |
| 10559490 | Dual-depth STI cavity extension and method of production thereof | Nigel Chan, Ming-Cheng Chang | 2020-02-11 |
| 10522555 | Semiconductor devices including Si/Ge active regions with different Ge concentrations | Gunter Grasshoff, Carsten Peters | 2019-12-31 |
| 10483154 | Front-end-of-line device structure and method of forming such a front-end-of-line device structure | Marcus Wolf, Carsten Peters, Markus Lenski, Loic Gaben | 2019-11-19 |
| 10418380 | High-voltage transistor device with thick gate insulation layers | Nigel Chan, Nilesh Kenkare | 2019-09-17 |
| 10396084 | Semiconductor devices including self-aligned active regions for planar transistor architecture | Nigel Chan, Nilesh Kenkare, Hongsik Yoon | 2019-08-27 |
| 10340359 | Gate structure with dual width electrode layer | — | 2019-07-02 |
| 10319827 | High voltage transistor using buried insulating layer as gate dielectric | Nigel Chan | 2019-06-11 |
| 10304683 | Early gate silicidation in transistor elements | — | 2019-05-28 |
| 10283365 | Technique and related semiconductor devices based on crystalline semiconductor material formed on the basis of deposited amorphous semiconductor material | — | 2019-05-07 |
| 10199259 | Technique for defining active regions of semiconductor devices with reduced lithography effort | Michael Zier | 2019-02-05 |
| 10177163 | SOI-based floating gate memory cell | Nigel Chan | 2019-01-08 |
| 10157996 | Methods for forming integrated circuits that include a dummy gate structure | Jan Hoentschel, Nigel Chan, Sven Beyer | 2018-12-18 |
| 10103224 | Semiconductor structure including a trench capping layer | Steffen Sichler | 2018-10-16 |
| 9953876 | Method of forming a semiconductor device structure and semiconductor device structure | Hans-Juergen Thees | 2018-04-24 |
| 9923076 | Gate patterning for AC and DC performance boost | — | 2018-03-20 |
| 9847347 | Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof | Nilesh Kenkare, Nigel Chan | 2017-12-19 |