Issued Patents All Time
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10483154 | Front-end-of-line device structure and method of forming such a front-end-of-line device structure | Elliot John Smith, Marcus Wolf, Carsten Peters, Loic Gaben | 2019-11-19 |
| 9646838 | Method of forming a semiconductor structure including silicided and non-silicided circuit elements | Dominic Thurmer, Sven Metzger, Joachim Patzer | 2017-05-09 |
| 9184260 | Methods for fabricating integrated circuits with robust gate electrode structure protection | Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar | 2015-11-10 |
| 8987144 | High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer | Stephan Kronholz, Hans-Juergen Thees | 2015-03-24 |
| 8987103 | Multi-step deposition of a spacer material for reducing void formation in a dielectric material of a contact level of a semiconductor device | Kerstin Ruttloff, Volker Jaschke, Frank Seliger, Ralf Otterbach | 2015-03-24 |
| 8969916 | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode | Stephan Kronholz, Vassilios Papageorgiou | 2015-03-03 |
| 8871586 | Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material | Thilo Scheiper, Jan Hoentschel, Rolf Stephan | 2014-10-28 |
| 8847404 | Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules | Stephan Kronholz, Ralf Richter | 2014-09-30 |
| 8847205 | Spacer for a gate electrode having tensile stress and a method of forming the same | Hartmut Ruelke, Katja Huy | 2014-09-30 |
| 8835209 | Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas | Stephan Kronholz, Gunda Beernink | 2014-09-16 |
| 8835298 | NiSi rework procedure to remove platinum residuals | Sivakumar KUMARASAMY, Clemens Fitz, Jochen Willi. Poth, Kristin Schupke | 2014-09-16 |
| 8828819 | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode | Stephen Kronholz, Vassilios Papageorgiou | 2014-09-09 |
| 8815674 | Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions | Berthold Reimer, Bastian Haussdoerfer, Ardechir Pakfar | 2014-08-26 |
| 8772843 | Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices | Stephan Kronholz, Kerstin Ruttloff, Volker Jaschke | 2014-07-08 |
| 8765586 | Methods of forming metal silicide regions on semiconductor devices | Clemens Fitz, Peter Baars | 2014-07-01 |
| 8765559 | Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material | Stephan Kronholz, Gunda Beernink, Frank Seliger, Frank Richter | 2014-07-01 |
| 8765542 | Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions | Joachim Patzer, Frank Seliger, Stephan Kronholz | 2014-07-01 |
| 8735270 | Method for making high-K metal gate electrode structures by separate removal of placeholder materials | Klaus Hempel, Sven Beyer, Stephan Kruegel | 2014-05-27 |
| 8652917 | Superior stability of characteristics of transistors having an early formed high-K metal gate | Stephan Kronholz, Nadja Zakowsky | 2014-02-18 |
| 8564120 | Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside | Anthony Mowry, David Gerald Farber, Fred N. Hause | 2013-10-22 |
| 8557667 | Spacer for a gate electrode having tensile stress and a method of forming the same | Hartmut Rülke, Katja Huy | 2013-10-15 |
| 8530894 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Anthony Mowry, Casey Scott, Vassilios Papageorgiou, Andy Wei, Andreas Gehring | 2013-09-10 |
| 8507351 | Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation | Anthony Mowry, Guido Koerner, Ralf Otterbach | 2013-08-13 |
| 8445378 | Method of manufacturing a CMOS device including molecular storage elements in a via level | Stephan Kronholz, Ralf Richter | 2013-05-21 |
| 8440561 | Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules | Stephan Kronholz, Ralf Richter | 2013-05-14 |