Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10559593 | Field-effect transistors with a grown silicon-germanium channel | Carsten Metze, Simeon Morvan | 2020-02-11 |
| 9842762 | Method of manufacturing a semiconductor wafer having an SOI configuration | Boris Bayha | 2017-12-12 |
| 9054041 | Methods for etching dielectric materials in the fabrication of integrated circuits | Johannes von Kluge | 2015-06-09 |
| 8951901 | Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry | Sven Beyer, Falk Graetsch | 2015-02-10 |
| 8815674 | Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions | Markus Lenski, Bastian Haussdoerfer, Ardechir Pakfar | 2014-08-26 |
| 8716136 | Method of forming a semiconductor structure including a wet etch process for removing silicon nitride | Johannes von Kluge, Sven Beyer | 2014-05-06 |
| 8703620 | Methods for PFET fabrication using APM solutions | Joanna Wasyluk, Stephan Kronholz, Sven Metzger, Gregory Nowling, John Foster +1 more | 2014-04-22 |
| 8658543 | Methods for pFET fabrication using APM solutions | Joanna Wasyluk, Stephan Kronholz, Yew Tuck Chow, Richard J. Carter, Kai Tern Sih | 2014-02-25 |
| 8580133 | Methods of controlling the etching of silicon nitride relative to silicon dioxide | Claudia Wolf | 2013-11-12 |
| 8524591 | Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma | Sven Beyer, Rick Carter, Andreas Hellmich | 2013-09-03 |
| 8445344 | Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning | Richard J. Carter, Falk Graetsch, Martin Trentzsch, Sven Beyer, Robert Binder +1 more | 2013-05-21 |
| 8357575 | Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers | Klaus Hempel, Patrick Press, Vivien Schroeder, Johannes Groschopf | 2013-01-22 |
| 8283232 | Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing | Sven Beyer, Falk Graetsch | 2012-10-09 |
| 8247281 | Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers | Klaus Hempel, Patrick Press, Vivien Schroeder, Johannes Groschopf | 2012-08-21 |
| 8048748 | Reducing contamination in a process flow of forming a channel semiconductor alloy in a semiconductor device | Stephan Kronholz, Richard J. Carter, Fernando Luiz Koch, Gisela Schammler | 2011-11-01 |