Issued Patents All Time
Showing 1–25 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12404111 | Roller conveyor | Erwin Mans, Jürgen Zinn, Kai Lubomierski | 2025-09-02 |
| 12319514 | Conveyor device | Kai Lubomierski, Jürgen Zinn, Erwin Mans | 2025-06-03 |
| 11543076 | Flushable pressure vessel | Thomas Kluge, Elmar Ritzerfeld, Erich Josef Titz | 2023-01-03 |
| 11408564 | Self-sealing valve connection for pressure vessels | Edwin Zimmermann, Wilhelm Krath, Josef Mulheims | 2022-08-09 |
| 9548378 | Epitaxial channel formation methods and structures | Nadja Zakowsky, Yew Tuck Chow | 2017-01-17 |
| 9484459 | Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer | Peter Javorka, Gunda Beernink | 2016-11-01 |
| 9269631 | Integration of semiconductor alloys in PMOS and NMOS transistors by using a common cavity etch process | Vassilios Papageorgiou | 2016-02-23 |
| 9263582 | Strain engineering in semiconductor devices by using a piezoelectric material | Maciej Wiatr | 2016-02-16 |
| 9224863 | Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer | Peter Javorka, Gunda Beernink | 2015-12-29 |
| 9029919 | Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer | Joachim Patzer | 2015-05-12 |
| 9018065 | Horizontal epitaxy furnace for channel SiGe formation | Joanna Wasyluk, Yew Tuck Chow, Lindarti Purwaningsih, Ines Becker | 2015-04-28 |
| 9006835 | Transistor with embedded Si/Ge material having reduced offset and superior uniformity | Peter Javorka, Roman Boschke | 2015-04-14 |
| 8987144 | High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer | Markus Lenski, Hans-Juergen Thees | 2015-03-24 |
| 8969916 | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode | Markus Lenski, Vassilios Papageorgiou | 2015-03-03 |
| 8969190 | Methods of forming a layer of silicon on a layer of silicon/germanium | Joachim Patzer | 2015-03-03 |
| 8939765 | Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth | Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger | 2015-01-27 |
| 8884379 | Strain engineering in semiconductor devices by using a piezoelectric material | Maciej Wiatr | 2014-11-11 |
| 8847404 | Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules | Markus Lenski, Ralf Richter | 2014-09-30 |
| 8835209 | Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas | Gunda Beernink, Markus Lenski | 2014-09-16 |
| 8836047 | Reducing defect rate during deposition of a channel semiconductor alloy into an in situ recessed active region | Peter Javorka, Maciej Wiatr | 2014-09-16 |
| 8828816 | PMOS threshold voltage control by germanium implantation | Peter Javorka | 2014-09-09 |
| 8809151 | Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy | Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper | 2014-08-19 |
| 8796080 | Methods of epitaxially forming materials on transistor devices | Hans-Juergen Thees, Peter Javorka | 2014-08-05 |
| 8772843 | Oxide deposition by using a double liner approach for reducing pattern density dependence in sophisticated semiconductor devices | Markus Lenski, Kerstin Ruttloff, Volker Jaschke | 2014-07-08 |
| 8765559 | Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material | Gunda Beernink, Markus Lenski, Frank Seliger, Frank Richter | 2014-07-01 |