Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9490344 | Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process | Stefan Flachowsky, Jan Hoentschel | 2016-11-08 |
| 9490361 | Canyon gate transistor and methods for its fabrication | Stefan Flachowsky | 2016-11-08 |
| 9490189 | Semiconductor device comprising a stacked die configuration including an integrated peltier element | Uwe Griebenow, Jan Hoentschel, Sven Beyer | 2016-11-08 |
| 9425052 | Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures | Jan Hoentschel, Steven Langdon | 2016-08-23 |
| 9184095 | Contact bars with reduced fringing capacitance in a semiconductor device | Sven Beyer, Uwe Griebenow, Jan Hoentschel, Andy Wei | 2015-11-10 |
| 9082662 | SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask | Stefan Flachowsky | 2015-07-14 |
| 9054207 | Field effect transistors for a flash memory comprising a self-aligned charge storage region | Sven Beyer, Uwe Griebenow, Jan Hoentschel | 2015-06-09 |
| 9048336 | Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures | Jan Hoentschel, Steven Langdon | 2015-06-02 |
| 9040403 | Methods for fabricating integrated circuits having gate to active and gate to gate interconnects | Stefan Flachowsky, Andy Wei | 2015-05-26 |
| 9023696 | Method of forming contacts for devices with multiple stress liners | Peter Baars, Marco Lepper | 2015-05-05 |
| 8987104 | Method of forming spacers that provide enhanced protection for gate electrode structures | Peter Baars, Sven Beyer, Jan Hoentschel | 2015-03-24 |
| 8975704 | Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky | 2015-03-10 |
| 8936977 | Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations | Jan Hoentschel, Shiang Yang Ong, Stefan Flachowsky | 2015-01-20 |
| 8916433 | Superior integrity of high-k metal gate stacks by capping STI regions | Peter Baars, Sven Beyer | 2014-12-23 |
| 8872285 | Metal gate structure for semiconductor devices | Carsten Grass, Richard J. Carter, Martin Trentzsch | 2014-10-28 |
| 8871586 | Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material | Jan Hoentschel, Markus Lenski, Rolf Stephan | 2014-10-28 |
| 8815736 | Methods of forming metal silicide regions on semiconductor devices using different temperatures | Peter Javorka, Stefan Flachowsky, Clemens Fitz | 2014-08-26 |
| 8809151 | Transistor comprising an embedded sigma shaped sequentially formed semiconductor alloy | Stefan Flachowsky, Stephan Kronholz, Jan Hoentschel | 2014-08-19 |
| 8790973 | Workfunction metal stacks for a final metal gate | Jan Hoentschel | 2014-07-29 |
| 8786027 | Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage | Uwe Griebenow, Jan Hoentschel, Sven Beyer | 2014-07-22 |
| 8759922 | Full silicidation prevention via dual nickel deposition approach | Peter Javorka, Stefan Flachowsky | 2014-06-24 |
| 8759960 | Semiconductor device comprising a stacked die configuration including an integrated Peltier element | Uwe Griebenow, Jan Hoentschel, Sven Beyer | 2014-06-24 |
| 8748281 | Enhanced confinement of sensitive materials of a high-K metal gate electrode structure | Jan Hoentschel, Sven Beyer, Uwe Griebenow | 2014-06-10 |
| 8722498 | Self-aligned fin transistor formed on a bulk substrate by late fin etch | Andy Wei | 2014-05-13 |
| 8722500 | Methods for fabricating integrated circuits having gate to active and gate to gate interconnects | Stefan Flachowsky, Andy Wei | 2014-05-13 |