PJ

Peter Javorka

Globalfoundries: 56 patents #36 of 4,424Top 1%
AM AMD: 5 patents #2,159 of 9,279Top 25%
GU Globalfoundries U.S.: 2 patents #206 of 665Top 35%
Overall (All Time): #35,493 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 25 most recent of 63 patents

Patent #TitleCo-InventorsDate
12328926 Structures for a field-effect transistor that include a spacer structure Dominik Martin Kleimaier, Ruchil Kumar Jain, Jan Höntschel, Steven Langdon, Felix Holzmüller 2025-06-10
11387364 Transistor with phase transition material region between channel region and each source/drain region Avinash Lahgere, Prashanth Paramahans Manik, Ali Icel, Mohit Bajaj 2022-07-12
10643885 FDSOI channel control by implanted high-k buried oxide Philipp Steinmann 2020-05-05
10340380 Three-dimensional transistor with improved channel mobility Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2019-07-02
10049917 FDSOI channel control by implanted high-K buried oxide Philipp Steinmann 2018-08-14
9876111 Method of forming a semiconductor device structure using differing spacer widths and the resulting semiconductor device structure Steffen Sichler, Juergen Faul, Sylvain Baudot, Thorsten Kammler 2018-01-23
9484459 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer Stephan Kronholz, Gunda Beernink 2016-11-01
9472642 Method of forming a semiconductor device structure and such a semiconductor device structure Jan Hoentschel, Stefan Flachowsky, Ralf Richter 2016-10-18
9412848 Methods of forming a complex GAA FET device at advanced technology nodes Ralf Richter, Jan Hoentschel, Stefan Flachowsky 2016-08-09
9412859 Contact geometry having a gate silicon length decoupled from a transistor length Ralf Richter, Jan Hoentschel, Stefan Flachowsky 2016-08-09
9406565 Methods for fabricating integrated circuits with semiconductor substrate protection Ralf Richter, Jan Hoentschel 2016-08-02
9401423 Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer Stefan Flachowsky 2016-07-26
9391176 Multi-gate FETs having corrugated semiconductor stacks and method of forming the same Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2016-07-12
9373720 Three-dimensional transistor with improved channel mobility Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2016-06-21
9373509 FINFET doping method with curvilnear trajectory implantation beam path Ralf Richter, Stefan Flachowsky, Jan Hoentschel 2016-06-21
9349734 Selective FuSi gate formation in gate first CMOS technologies Stefan Flachowsky, Gerd Zschätzsch 2016-05-24
9343374 Efficient main spacer pull back process for advanced VLSI CMOS technologies Jan Hoentschel, Stefan Flachowsky, Ralf Richter 2016-05-17
9224863 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer Stephan Kronholz, Gunda Beernink 2015-12-29
9224655 Methods of removing gate cap layers in CMOS applications Ralf Richter, Stefan Flachowsky, Jan Hoentschel 2015-12-29
9177803 HK/MG process flows for P-type semiconductor devices Juergen Faul, Ralf Richter, Jan Hoentschel 2015-11-03
9129843 Integrated inductor Stefan Flachowsky, Ralf Richter, Jan Hoentschel 2015-09-08
9093526 Methods of forming a sidewall spacer having a generally triangular shape and a semiconductor device having such a spacer Juergen Faul, Bastian Haussdoerfer 2015-07-28
9082876 Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection Ralf Richter, Stefan Flachowsky 2015-07-14
9076818 Semiconductor device fabrication methods Andreas Kurz, Sergej Mutas, Clemens Wündisch 2015-07-07
9054044 Method for forming a semiconductor device and semiconductor device structures Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2015-06-09