TS

Thilo Scheiper

Globalfoundries: 67 patents #29 of 4,424Top 1%
GP Globalfoundries Singapore Pte.: 3 patents #212 of 828Top 30%
AM AMD: 2 patents #3,994 of 9,279Top 45%
📍 Dresden, DE: #6 of 3,254 inventorsTop 1%
Overall (All Time): #27,971 of 4,157,543Top 1%
72
Patents All Time

Issued Patents All Time

Showing 51–72 of 72 patents

Patent #TitleCo-InventorsDate
8481374 Semiconductor element comprising a low variation substrate diode — 2013-07-09
8476131 Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same Stefan Flachowsky, Ralf Illgen, Ricardo P. Mikalo 2013-07-02
8455314 Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage Uwe Griebenow, Jan Hoentschel, Sven Beyer 2013-06-04
8450163 Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach Sven Beyer, Klaus Hempel, Roland Stejskal, Andy Wei, Andreas Kurz +2 more 2013-05-28
8426266 Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices Jan Hoentschel, Andreas Kurz, Uwe Griebenow 2013-04-23
8409942 Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition Sven Beyer, Uwe Griebenow, Jan Hoentschel 2013-04-02
8404550 Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement Sven Beyer, Andy Wei, Jan Hoentschel 2013-03-26
8377773 Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask Peter Baars 2013-02-19
8357604 Work function adjustment in high-k gate stacks for devices of different threshold voltage Jan Hoentschel, Sven Beyer 2013-01-22
8349695 Work function adjustment in high-k gate stacks including gate dielectrics of different thickness Andy Wei, Martin Trentzsch 2013-01-08
8329531 Strain memorization in strained SOI substrates of semiconductor devices Jan Hoentschel, Sven Beyer, Uwe Griebenow 2012-12-11
8329551 Semiconductor device substrate with embedded stress region, and related fabrication methods Stefan Flachowsky, Jan Hoentschel 2012-12-11
8324041 Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors Stefan Flachowsky, Jan Hoentschel 2012-12-04
8318564 Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation Sven Beyer, Jan Hoentschel, Uwe Griebenow 2012-11-27
8241977 Short channel transistor with reduced length variation by using amorphous electrode material during implantation Andy Wei, Sven Beyer 2012-08-14
8232188 High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning Sven Beyer, Klaus Hempel, Stefanie Steiner 2012-07-31
8198152 Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials Sven Beyer, Jan Hoentschel, Uwe Griebenow 2012-06-12
8143132 Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime Jan Hoentschel, Sven Beyer 2012-03-27
8114746 Method for forming double gate and tri-gate transistors on a bulk substrate Andy Wei, Robert Neil Mulfinger, Thorsten Kammler 2012-02-14
8039342 Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal Uwe Griebenow, Jan Hoentschel, Andy Wei 2011-10-18
8026134 Recessed drain and source areas in combination with advanced silicide formation in transistors Uwe Griebenow, Andy Wei, Jan Hoentschel 2011-09-27
7943462 Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer Sven Beyer, Jan Hoentschel, Markus Lenski 2011-05-17