Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10121665 | Short-channel NFET device | Chi Dong Nguyen | 2018-11-06 |
| 9917016 | Integrated circuits and methods of forming the same with effective dummy gate cap removal | Dina H. Triyoso | 2018-03-13 |
| 9735012 | Short-channel nFET device | Chi Dong Nguyen | 2017-08-15 |
| 8735270 | Method for making high-K metal gate electrode structures by separate removal of placeholder materials | Sven Beyer, Markus Lenski, Stephan Kruegel | 2014-05-27 |
| 8735236 | High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology | Christopher M. Prindle, Rolf Stephan | 2014-05-27 |
| 8716120 | High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology | Andy Wei, Martin Mazur | 2014-05-06 |
| 8697530 | Drain/source extension structure of a field effect transistor with reduced boron diffusion | Ekkehard Pruefer, Ralf van Bentum, Stephan Kruegel | 2014-04-15 |
| 8673759 | Dry etch polysilicon removal for replacement gates | Chris M. Prindle, Andy Wei | 2014-03-18 |
| 8664103 | Metal gate stack formation for replacement gate technology | Andy Wei, Robert Binder, Joachim Metzger | 2014-03-04 |
| 8652956 | High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning | Sven Beyer, Thilo Scheiper, Stefanie Steiner | 2014-02-18 |
| 8450163 | Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach | Sven Beyer, Roland Stejskal, Andy Wei, Thilo Scheiper, Andreas Kurz +2 more | 2013-05-28 |
| 8440559 | Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer | Markus Lenski, Vivien Schroeder, Robert Binder, Joachim Metzger | 2013-05-14 |
| 8420519 | Methods for fabricating integrated circuits with controlled P-channel threshold voltage | Dina H. Triyoso, Elke Erben | 2013-04-16 |
| 8367495 | Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material | Sven Beyer, Markus Lenski, Richard J. Carter | 2013-02-05 |
| 8357575 | Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers | Patrick Press, Vivien Schroeder, Berthold Reimer, Johannes Groschopf | 2013-01-22 |
| 8324091 | Enhancing integrity of a high-k gate stack by confining a metal cap layer after deposition | Joachim Metzger, Robert Binder, Markus Lenski | 2012-12-04 |
| 8298894 | Work function adjustment in high-k metal gate electrode structures by selectively removing a barrier layer | Markus Lenski, Vivien Schroeder, Robert Binder, Joachim Metzger | 2012-10-30 |
| 8247281 | Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers | Patrick Press, Vivien Schroeder, Berthold Reimer, Johannes Groschopf | 2012-08-21 |
| 8232188 | High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning | Sven Beyer, Thilo Scheiper, Stefanie Steiner | 2012-07-31 |
| 8158486 | Trench isolation structure having different stress | Ralf van Bentum, Roland Stejskal | 2012-04-17 |
| 8048792 | Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material | Sven Beyer, Andreas Ott, Stephan Kruegel | 2011-11-01 |
| 7358150 | Trench isolation structure for a semiconductor device with reduced sidewall stress and a method of manufacturing the same | Stephan Kruegel, Ekkehard Pruefer | 2008-04-15 |