MM

Martin Mazur

Globalfoundries: 9 patents #393 of 4,424Top 9%
AM AMD: 8 patents #1,491 of 9,279Top 20%
📍 Pulsnitz, DE: #1 of 11 inventorsTop 10%
Overall (All Time): #275,137 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDate
9972634 Semiconductor device comprising a floating gate flash memory device Ralf Richter, Peter Krottenthaler 2018-05-15
9372392 Reticles for use in forming implant masking layers and methods of forming implant masking layers Dietmar Henke, Hans-Juergen Thees 2016-06-21
9281200 Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping Hans-Juergen Thees, Sven Beyer, Steffen Laufer 2016-03-08
8927407 Method of forming self-aligned contacts for a semiconductor device Peter Baars, Andy Wei, Erik Geiss 2015-01-06
8802360 Reticles for use in forming implant masking layers and methods of forming implant masking layers Henke Dietmar, Hans-Juergen Thees 2014-08-12
8716120 High-k metal gate electrode structures formed by reducing a gate fill aspect ratio in replacement gate technology Klaus Hempel, Andy Wei 2014-05-06
8258062 Cap layer removal in a high-K metal gate stack by using an etch process Ralf Richter, Frank Seliger 2012-09-04
7994059 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device Ralf Richter, Martin Gerhardt, Joerg Hohage 2011-08-09
7981740 Enhanced cap layer integrity in a high-K metal gate stack by using a hard mask for offset spacer patterning Markus Lenski, Kerstin Ruttloff, Frank Seliger, Ralf Otterbach 2011-07-19
7938973 Arc layer having a reduced flaking tendency and a method of manufacturing the same Ralf Richter, Joerg Hohage 2011-05-10
7887978 Method of detecting repeating defects in lithography masks on the basis of test substrates exposed under varying conditions Uwe Griebenow, Wolfram Grundke, Andre Poock 2011-02-15
7550396 Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device Kai Frohberg, Volker Grimm, Sven Mueller, Matthias Lehr, Ralf Richter +4 more 2009-06-23
7547561 Advanced process control model incorporating a target offset term Uwe Schulze, Andreas Becker 2009-06-16
7314793 Technique for controlling mechanical stress in a channel region by spacer removal Kai Frohberg, Matthias Schaller, Massud Aminpur, Roberto Klingler 2008-01-01
6936383 Method of defining the dimensions of circuit elements by using spacer deposition techniques Carsten Hartig, Georg Sulzer 2005-08-30
6759179 Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Khoi A. Phan, Jeffrey P. Erhardt, Jerry Cheng, Richard Bartlett, Anthony P. Coniglio +3 more 2004-07-06
6649525 Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Khoi A. Phan, Jeffrey P. Erhardt, Jerry Cheng, Richard Bartlett, Anthony P. Coniglio +3 more 2003-11-18