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USPTO Patent Rankings Data through Dec 31, 2025
JH

Joerg Hohage — 31 Patents

AMD: 25 patents #427 of 9,280Top 5%
Globalfoundries: 6 patents #578 of 4,424Top 15%
Dresden, DE: #44 of 3,254 inventorsTop 2%
Overall (All Time): #115,823 of 4,157,543Top 3%
31 Patents All Time
Joerg Hohage has been granted 31 US patents while listed as an inventor at AMD. The first was granted in 2002 and the most recent in September 2014. Joerg Hohage ranks #115,823 of 4,157,543 US inventors in our database (top 2.8%). Patent records list Joerg Hohage in Dresden, DE.

Issued Patents All Time

Showing 1–25 of 31 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8841140 Technique for forming a passivation layer without a terminal metal Tobias Letz, Matthias Lehr, Frank Kuechenmeister 2014-09-23 $5,345,000
8828888 Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer Matthias Lehr, Andreas Ott 2014-09-09 $2,134,000
8759232 Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress Hartmut Ruelke, Ralf Richter 2014-06-24 $2,752,000
8546274 Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material Michael Finken, Ralf Richter 2013-10-01 $6,159,000
8450172 Non-insulating stressed material layers in a contact level of semiconductor devices Ralf Richter, Hartmut Ruelke 2013-05-28 $3,942,000
8338284 Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer Kai Frohberg, Hartmut Ruelke, Volker Jaschke, Frank Seliger 2012-12-25
8211795 Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment Volker Kahlert, Hartmut Ruelke, Ulrich Mayer 2012-07-03 $6,918,000
8153524 Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices Oliver Aubel, Frank Feustel, Axel Preusse 2012-04-10 $5,913,000
8053354 Reduced wafer warpage in semiconductors by stress engineering in the metallization system Matthias Lehr, Frank Koschinsky 2011-11-08 $4,445,000
8034726 Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials Ralf Richter, Michael Finken, Heike Salz 2011-10-11 $4,727,000
7994059 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device Ralf Richter, Martin Gerhardt, Martin Mazur 2011-08-09 $3,614,000
7994072 Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device Michael Finken, Ralf Richter 2011-08-09 $3,614,000
7938973 Arc layer having a reduced flaking tendency and a method of manufacturing the same Ralf Richter, Martin Mazur 2011-05-10 $5,537,000
7906383 Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device Ralf Richter, Andy Wei, Manfred Horstmann 2011-03-15 $6,095,000
7875561 Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material Michael Finken, Ralf Richter 2011-01-25 $8,589,000
7867917 Etch stop layer for a metallization layer with enhanced adhesion, etch selectivity and hermeticity Matthias Lehr, Volker Kahlert 2011-01-11 $5,518,000
7858531 Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region Ralf Richter, Michael Finken, Jana Schlott 2010-12-28 $4,143,000
7678699 Method of forming an insulating capping layer for a copper metallization layer by using a silane reaction Matthias Lehr, Volker Kahlert 2010-03-16 $8,771,000
7608912 Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress Kai Frohberg, Thomas Werner 2009-10-27 $8,132,000
7550396 Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device Kai Frohberg, Volker Grimm, Sven Mueller, Matthias Lehr, Ralf Richter +4 more 2009-06-23 $21,858,000
7491638 Method of forming an insulating capping layer for a copper metallization layer Matthias Lehr, Volker Kahlert 2009-02-17 $4,823,000
7476626 Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity Matthias Lehr, Volker Kahlert 2009-01-13 $12,331,000
7396718 Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress Kai Frohberg, Matthias Schaller, Holger Schuehrer 2008-07-08 $10,607,000
7381602 Method of forming a field effect transistor comprising a stressed channel region Hartmut Ruelke, Kai Frohberg 2008-06-03 $5,507,000
7341903 Method of forming a field effect transistor having a stressed channel region Hartmut Ruelke, Kai Frohberg 2008-03-11 $39,863,000