Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
HR

Hartmut Ruelke — 32 Patents

AMD: 21 patents #538 of 9,280Top 6%
Globalfoundries: 11 patents #330 of 4,424Top 8%
Radebeul, DE: #1 of 243 inventorsTop 1%
Overall (All Time): #110,428 of 4,157,543Top 3%
32 Patents All Time
Hartmut Ruelke has been granted 32 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in September 2014. Hartmut Ruelke ranks #110,428 of 4,157,543 US inventors in our database (top 2.7%). Patent records list Hartmut Ruelke in Radebeul, DE.

Patents per Year

Patents granted per year, 2001 to 2014Bar chart with a peak of 5 patents in 2008.peak 52001: 2 patents20012002: 2 patents2003: 4 patents20032004: 2 patents2005: 2 patents20052006: 3 patents2008: 5 patents20082010: 1 patents2011: 2 patents20112012: 2 patents2013: 3 patents20132014: 4 patents2014

Issued Patents All Time

Showing 1–25 of 32 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8847205 Spacer for a gate electrode having tensile stress and a method of forming the same Katja Huy, Markus Lenski 2014-09-30 $1,660,000
8772178 Technique for forming a dielectric interlayer above a structure including closely spaced lines Christof Streck, Kai Frohberg 2014-07-08 $2,496,000
8759232 Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress Joerg Hohage, Ralf Richter 2014-06-24 $2,752,000
8741787 Increased density of low-K dielectric materials in semiconductor devices by applying a UV treatment Ulrich Mayer, Christof Streck 2014-06-03 $2,732,000
8609555 Increased stability of a complex material stack in a semiconductor device by providing fluorine enriched interfaces Christof Streck, Heinz-Juergen Voss 2013-12-17 $1,491,000
8450172 Non-insulating stressed material layers in a contact level of semiconductor devices Ralf Richter, Joerg Hohage 2013-05-28 $3,942,000
8415257 Enhanced adhesion of PECVD carbon on dielectric materials by providing an adhesion interface Volker Jaschke 2013-04-09 $4,395,000
8338284 Stress engineering in a contact level of semiconductor devices by stressed conductive layers and an isolation spacer Kai Frohberg, Volker Jaschke, Joerg Hohage, Frank Seliger 2012-12-25
8211795 Method of forming a dielectric cap layer for a copper metallization by using a hydrogen based thermal-chemical treatment Joerg Hohage, Volker Kahlert, Ulrich Mayer 2012-07-03 $6,918,000
8084088 Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers Katja Huy, Michael D. Turner 2011-12-27 $7,638,000
7998882 Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step Ulrich Mayer 2011-08-16 $3,370,000
7807233 Method of forming a TEOS cap layer at low temperature and reduced deposition rate Katja Huy, Karla Romero 2010-10-05 $25,101,000
7381660 Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness Larry Zhao, Jeremy I. Martin 2008-06-03 $5,507,000
7381602 Method of forming a field effect transistor comprising a stressed channel region Joerg Hohage, Kai Frohberg 2008-06-03 $5,507,000
7341903 Method of forming a field effect transistor having a stressed channel region Joerg Hohage, Kai Frohberg 2008-03-11 $39,863,000
7326646 Nitrogen-free ARC layer and a method of manufacturing the same Katja Huy, Sven Muehle 2008-02-05 $6,320,000
7314824 Nitrogen-free ARC/capping layer and method of manufacturing the same Kai Frohberg, Sven Muehle 2008-01-01
7030044 Method of forming a cap layer having anti-reflective characteristics on top of a low-k dielectric Joerg Hohage, Thomas Werner, Frank Mauersberger 2006-04-18 $11,889,000
7022602 Nitrogen-enriched low-k barrier layer for a copper metallization layer Joerg Hohage, Thomas Werner, Michael Kiene 2006-04-04 $14,413,000
6989601 Copper damascene with low-k capping layer and improved electromigration reliability Minh Van Ngo, Jeremy I. Martin 2006-01-24 $11,964,000
6927161 Low-k dielectric layer stack including an etch indicator layer for use in the dual damascene technique Christof Streck, Georg Sulzer 2005-08-09 $9,550,000
6893956 Barrier layer for a copper metallization layer including a low-k dielectric Joerg Hohage, Thomas Werner, Massud Aminpur 2005-05-17 $3,810,000
6797652 Copper damascene with low-k capping layer and improved electromigration reliability Minh Van Ngo, Jeremy I. Martin 2004-09-28 $1,915,000
6720242 Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer Gert Burbach, Frank Heinlein, Johannes Groschopf, Gotthard Jungnickel, Carsten Hartig 2004-04-13 $3,617,000
6599827 Methods of forming capped copper interconnects with improved electromigration resistance Minh Van Ngo, Steven C. Avanzino, Amit P. Marathe 2003-07-29 $3,092,000