Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AM

Amit P. Marathe — 58 Patents

AMD: 55 patents #117 of 9,280Top 2%
SLSpansion Llc.: 2 patents #309 of 769Top 45%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
INInseego: 1 patents #9 of 14Top 65%
Microsoft: 1 patents #24,968 of 40,388Top 65%
Sunnyvale, CA: #270 of 14,302 inventorsTop 2%
California: #6,228 of 386,348 inventorsTop 2%
Overall (All Time): #41,319 of 4,157,543Top 1%
58 Patents All Time
Amit P. Marathe has been granted 58 US patents while listed as an inventor at AMD. The first was granted in 2000 and the most recent in November 2022. Amit P. Marathe ranks #41,319 of 4,157,543 US inventors in our database (top 0.99%). Patent records list Amit P. Marathe in Sunnyvale, CA, US.

Patents per Year

Patents granted per year, 2000 to 2022Bar chart with a peak of 13 patents in 2002.peak 132000: 2 patents20002001: 1 patents2002: 13 patents20022003: 10 patents2004: 11 patents20042005: 6 patents2006: 5 patents20062007: 2 patents2008: 3 patents20082010: 1 patents2011: 1 patents20112013: 1 patents2016: 1 patents20162022: 1 patents2022

Issued Patents All Time

Showing 1–25 of 58 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11490812 Systems and methods for monitoring and detecting symptoms of infectious conditions 2022-11-08 $2,442,000
9495491 Reliability aware thermal design Kingsuk Maitra, Tung Thanh Nguyen, Brian K. Langendorf, Julia Purtell, Rune Hartung Jensen +1 more 2016-11-15 $54,363,000
8501504 Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer Kok Yong Yiang, Rick Francis, Van-Hung Pham 2013-08-06 $2,454,000
8022716 Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance Kok Yong Yiang, Rick Francis, Van-Hung Pham 2011-09-20 $13,504,000
7755194 Composite barrier layers with controlled copper interface surface roughness Connie P. Wang, Christy Mei-Chu Woo, Paul L. King 2010-07-13 $9,965,000
7451411 Integrated circuit design system Christine Hau-Riege 2008-11-11 $5,286,000
7379924 Quantifying and predicting the impact of line edge roughness on device reliability and performance Calvin T. Gabriel 2008-05-27 $41,100,000
7340360 Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness John H. Zhang, Kurt Taylor, Eugene Zhao, Rolf Geilenkeuser, Joerg-Oliver Weidner 2008-03-04 $9,869,000
7310155 Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures Luigi Capodieci, Bhanwar Singh, Ramkumar Subramanian 2007-12-18 $12,803,000
7288782 Use of Ta-capped metal line to improve formation of memory element films Steven C. Avanzino 2007-10-30
7155359 Determination of device failure characteristic Hyeon-Seag Kim, Kurt Taylor 2006-12-26 $21,181,000
7146588 Predicting EM reliability by decoupling extrinsic and intrinsic sigma Darrell M. Erb 2006-12-05 $14,281,000
7084062 Use of Ta-capped metal line to improve formation of memory element films Steven C. Avanzino 2006-08-01
7033940 Method of forming composite barrier layers with controlled copper interface surface roughness Connie P. Wang, Christy Mei-Chu Woo, Paul L. King 2006-04-25 $9,950,000
7026225 Semiconductor component and method for precluding stress-induced void formation in the semiconductor component Christine Hau-Riege, John Sanchez 2006-04-11 $9,016,000
6952052 Cu interconnects with composite barrier layers for wafer-to-wafer uniformity Connie P. Wang, Christy Mei-Chu Woo 2005-10-04 $16,745,000
6939803 Method for forming conductor reservoir volume for integrated circuit interconnects Pin-Chin Connie Wang, Christy Mei-Chu Woo 2005-09-06 $13,866,000
6897476 Test structure for determining electromigration and interlayer dielectric failure Hyeon-Seag Kim, Seung-Hyun Rhee, Christine Hau-Riege 2005-05-24 $6,015,000
6867056 System and method for current-enhanced stress-migration testing of interconnect Christine Hau-Riege 2005-03-15 $4,259,000
6858511 Method of semiconductor via testing 2005-02-22 $8,271,000
6856160 Maximum VCC calculation method for hot carrier qualification Hyeon-Seag Kim, Nian Yang, Tien-Chun Yang 2005-02-15 $5,967,000
6825684 Hot carrier oxide qualification method Hyeon-Seag Kim, Nian Yang, Tien-Chun Yang 2004-11-30 $7,368,000
6822437 Interconnect test structure with slotted feeder lines to prevent stress-induced voids Christine Hau-Riege, John Sanchez 2004-11-23 $3,336,000
6822473 Determination of permeability of layer material within interconnect Christine Hau-Riege, Stefan Hau-Riege 2004-11-23 $3,336,000
6770847 Method and system for Joule heating characterization Huade Walter Yao, Van-Hung Pham 2004-08-03 $1,898,000