| 7696092 |
Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect |
Sergey Lopatin, Paul R. Besser |
2010-04-13 |
$12,774,000 |
| 7169706 |
Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition |
Sergey Lopatin, Paul R. Besser, Alline F. Myers, Jeremias D. Romero, Minh Quoc Tran +1 more |
2007-01-30 |
$15,947,000 |
| 6992004 |
Implanted barrier layer to improve line reliability and method of forming same |
Paul R. Besser, Matthew S. Buynoski, Minh Quoc Tran, Lu You, Sergey Lopatin +1 more |
2006-01-31 |
$15,487,000 |
| 6979903 |
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
Steven C. Avanzino, Minh Van Ngo |
2005-12-27 |
$8,074,000 |
| 6939803 |
Method for forming conductor reservoir volume for integrated circuit interconnects |
Amit P. Marathe, Christy Mei-Chu Woo |
2005-09-06 |
$13,866,000 |
| 6893955 |
Manufacturing seedless barrier layers in integrated circuits |
Sergey Lopatin |
2005-05-17 |
$3,810,000 |
| 6861349 |
Method of forming an adhesion layer with an element reactive with a barrier layer |
Sergey Lopatin, Paul R. Besser, Matthew S. Buynoski |
2005-03-01 |
$6,648,000 |
| 6841473 |
Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap |
Steven C. Avanzino |
2005-01-11 |
$4,696,000 |
| 6833625 |
Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect |
Fei Wang |
2004-12-21 |
$5,396,000 |
| 6831003 |
Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration |
Richard J. Huang, Darrell M. Erb |
2004-12-14 |
$6,995,000 |
| 6815340 |
Method of forming an electroless nucleation layer on a via bottom |
Sergey Lopatin, Paul R. Besser, Matthew S. Buynoski |
2004-11-09 |
$3,568,000 |
| 6710452 |
Coherent diffusion barriers for integrated circuit interconnects |
Matthew S. Buynoski, Suzette K. Pangrle, Amit P. Marathe |
2004-03-23 |
$3,151,000 |
| 6674170 |
Barrier metal oxide interconnect cap in integrated circuits |
Minh Van Ngo |
2004-01-06 |
$4,179,000 |
| 6663787 |
Use of ta/tan for preventing copper contamination of low-k dielectric layers |
Lu You, Christy Mei-Chu Woo |
2003-12-16 |
$3,174,000 |
| 6664185 |
Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect |
Fei Wang |
2003-12-16 |
$3,174,000 |
| 6656836 |
Method of performing a two stage anneal in the formation of an alloy interconnect |
Paul R. Besser |
2003-12-02 |
$4,088,000 |
| 6657303 |
Integrated circuit with low solubility metal-conductor interconnect cap |
Steven C. Avanzino |
2003-12-02 |
$4,088,000 |
| 6649034 |
Electro-chemical metal alloying for semiconductor manufacturing |
Minh Quoc Tran, Amit P. Marathe |
2003-11-18 |
$4,875,000 |
| 6642145 |
Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
Steven C. Avanzino, Minh Van Ngo |
2003-11-04 |
$3,831,000 |
| 6621290 |
Characterization of barrier layers in integrated circuit interconnects |
Amit P. Marathe |
2003-09-16 |
$3,735,000 |
| 6617176 |
METHOD OF DETERMINING BARRIER LAYER EFFECTIVENESS FOR PREVENTING METALLIZATION DIFFUSION BY FORMING A TEST SPECIMEN DEVICE AND USING A METAL PENETRATION MEASUREMENT TECHNIQUE FOR FABRICATING A PRODUCTION SEMICONDUCTOR DEVICE AND A TEST SPECIMEN DEVICE THEREBY FORMED |
John Sanchez, Christy Mei-Chu Woo, Paul R. Besser |
2003-09-09 |
$4,832,000 |
| 6589408 |
Non-planar copper alloy target for plasma vapor deposition systems |
Paul R. Besser, Sergey Lopatin, Minh Quoc Tran |
2003-07-08 |
$2,679,000 |
| 6590288 |
Selective deposition in integrated circuit interconnects |
Christy Mei-Chu Woo, Amit P. Marathe |
2003-07-08 |
$2,679,000 |
| 6573179 |
Forming a strong interface between interconnect and encapsulation to minimize electromigration |
Lu You |
2003-06-03 |
$3,251,000 |
| 6566248 |
Graphoepitaxial conductor cores in integrated circuit interconnects |
Minh Quoc Tran |
2003-05-20 |
$2,116,000 |
