Issued Patents All Time
Showing 25 most recent of 212 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11075339 | Correlated electron material (CEM) devices with contact region sidewall insulation | Ming He, Jingyan Zhang, Manuj Rathor | 2021-07-27 |
| 10854811 | Formation of correlated electron material (CEM) devices with restored sidewall regions | Ming He, Jolanta Bozena Celinska | 2020-12-01 |
| 10833271 | Method for fabrication of a CEM device | Ming He | 2020-11-10 |
| 10672982 | Fabrication of correlated electron material (CEM) devices | Ming He, Jingyan Zhang, Manuj Rathor | 2020-06-02 |
| 10566527 | Method for fabrication of a CEM device | Ming He | 2020-02-18 |
| 9607904 | Atomic layer deposition of HfAlC as a metal gate workfunction material in MOS devices | Albert S. Lee, Kisik Choi, Edward Haywood, Hoon Kim, Salil Mujumdar | 2017-03-28 |
| 9553031 | Method for integrating germanides in high performance integrated circuits | Thorsten Lill | 2017-01-24 |
| 9515156 | Air gap spacer integration for improved fin device performance | Bart J. van Schravendijk, Yoshie Kimura, Gerardo Delgadino, Harald Orkorn-Schmidt, Dengliang Yang | 2016-12-06 |
| 9484251 | Contact integration for reduced interface and series contact resistance | William Crew, Sanjay Gopinath | 2016-11-01 |
| 9362283 | Gate structures for transistor devices for CMOS applications and products | Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty +6 more | 2016-06-07 |
| 9269615 | Multi-layer barrier layer for interconnect structure | Vivian W. Ryan, Xunyuan Zhang | 2016-02-23 |
| 9202758 | Method for manufacturing a contact for a semiconductor component and related structure | Minh Van Ngo, Connie P. Wang, Jinsong Yin, Hieu Pham | 2015-12-01 |
| 9196475 | Methods for fabricating integrated circuits including fluorine incorporation | Bongki Lee, Kevin Kashefi, Olov Karlsson, Ashish Bodke, Ratsamee Limdulpaiboon +2 more | 2015-11-24 |
| 9142633 | Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures | Mark V. Raymond, Valli Arunachalam, Hoon Kim | 2015-09-22 |
| 9105497 | Methods of forming gate structures for transistor devices for CMOS applications | Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty +6 more | 2015-08-11 |
| 9076792 | Multi-layer barrier layer stacks for interconnect structures | Vivian W. Ryan, Xunyuan Zhang | 2015-07-07 |
| 8778789 | Methods for fabricating integrated circuits having low resistance metal gate structures | Sean Xuan Lin, Valli Arunachalam | 2014-07-15 |
| 8772158 | Multi-layer barrier layer stacks for interconnect structures | Vivian W. Ryan, Xunyuan Zhang | 2014-07-08 |
| 8728931 | Multi-layer barrier layer for interconnect structure | Vivian W. Ryan, Xunyuan Zhang | 2014-05-20 |
| 8723321 | Copper interconnects with improved electromigration lifetime | Christy Mei-Chu Woo, Jun Zhai, Kok Yong Yiang, Richard C. Blish, II, Christine Hau-Riege | 2014-05-13 |
| 8709941 | Method for forming contact in an integrated circuit | — | 2014-04-29 |
| 8703620 | Methods for PFET fabrication using APM solutions | Joanna Wasyluk, Stephan Kronholz, Berthold Reimer, Sven Metzger, Gregory Nowling +1 more | 2014-04-22 |
| 8691689 | Methods for fabricating integrated circuits having low resistance device contacts | Sean Xuan Lin, Valli Arunachalam | 2014-04-08 |
| 8623758 | Subtractive metal multi-layer barrier layer for interconnect structure | Vivian W. Ryan, Xunyuan Zhang | 2014-01-07 |
| 8330235 | Method to reduce mol damage on NiSi | Karthik Ramani | 2012-12-11 |