Issued Patents All Time
Showing 51–75 of 212 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7309650 | Memory device having a nanocrystal charge storage region and method | Connie P. Wang, Lu You, Zoran Krivokapic, Suzette K. Pangrle | 2007-12-18 |
| 7307322 | Ultra-uniform silicide system in integrated circuit technology | Robert J. Chiu, Jeffrey P. Patton, Minh Van Ngo | 2007-12-11 |
| 7217660 | Method for manufacturing a semiconductor component that inhibits formation of wormholes | Connie P. Wang, Jinsong Yin, Hieu Pham, Minh Van Ngo | 2007-05-15 |
| 7169706 | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition | Sergey Lopatin, Alline F. Myers, Jeremias D. Romero, Minh Quoc Tran, Lu You +1 more | 2007-01-30 |
| 7151020 | Conversion of transition metal to silicide through back end processing in integrated circuit technology | Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler, Robert J. Chiu, Errol Todd Ryan +3 more | 2006-12-19 |
| 7132352 | Method of eliminating source/drain junction spiking, and device produced thereby | Simon S. Chan, Jeffrey P. Patton | 2006-11-07 |
| 7071086 | Method of forming a metal gate structure with tuning of work function by silicon incorporation | Christy Mei-Chu Woo, Minh Van Ngo, James Pan, Jinsong Yin | 2006-07-04 |
| 7060571 | Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric | Minh Van Ngo, Christy Mei-Chu Woo, James Pan, Jinsong Yin | 2006-06-13 |
| 7049666 | Low power pre-silicide process in integrated circuit technology | Robert J. Chiu, Jeffrey P. Patton, Minh Van Ngo | 2006-05-23 |
| 7033888 | Engineered metal gate electrode | James Pan, Christy Mei-Chu Woo, Minh Van Ngo, Jinsong Yin | 2006-04-25 |
| 7005376 | Ultra-uniform silicides in integrated circuit technology | Robert J. Chiu, Jeffrey P. Patton, Minh Van Ngo | 2006-02-28 |
| 7005357 | Low stress sidewall spacer in integrated circuit technology | Minh Van Ngo, Simon S. Chan, Paul L. King, Errol Todd Ryan, Robert J. Chiu | 2006-02-28 |
| 7001837 | Semiconductor with tensile strained substrate and method of making the same | Minh Van Ngo, Ming-Ren Lin, Haihong Wang | 2006-02-21 |
| 6992004 | Implanted barrier layer to improve line reliability and method of forming same | Matthew S. Buynoski, Minh Quoc Tran, Pin-Chin Connie Wang, Lu You, Sergey Lopatin +1 more | 2006-01-31 |
| 6979642 | Method of self-annealing conductive lines that separates grain size effects from alloy mobility | Matthew S. Buynoski, Connie P. Wang, Minh Quoc Tran | 2005-12-27 |
| 6969678 | Multi-silicide in integrated circuit technology | Robert J. Chiu, Simon S. Chan, Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler +1 more | 2005-11-29 |
| 6967160 | Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness | Eric N. Paton, Simon S. Chan, Fred N. Hause | 2005-11-22 |
| 6951220 | Method of decontaminating equipment | Farzad Arasnia, Minh Van Ngo, Qi Xiang | 2005-10-04 |
| 6943569 | Method, system and apparatus to detect defects in semiconductor devices | Laura Pressley, David E. Brown, Travis R. Lewis, Edward E. Ehrichs | 2005-09-13 |
| 6927162 | Method of forming a contact in a semiconductor device with formation of silicide prior to plasma treatment | Wen Yu, Jinsong Yin, Connie P. Wang, Keizaburo Yoshie | 2005-08-09 |
| 6897144 | Cu capping layer deposition with improved integrated circuit reliability | Minh Van Ngo, Larry Zhao | 2005-05-24 |
| 6893910 | One step deposition method for high-k dielectric and metal gate electrode | Christy Mei-Chu Woo, Minh Van Ngo, James Pan, Jinsong Yin | 2005-05-17 |
| 6878592 | Selective epitaxy to improve silicidation | Minh Van Ngo, Qi Xiang, Eric N. Paton | 2005-04-12 |
| 6873051 | Nickel silicide with reduced interface roughness | Eric N. Paton, Simon S. Chan, Fred N. Hause | 2005-03-29 |
| 6867428 | Strained silicon NMOS having silicon source/drain extensions and method for its fabrication | Eric N. Paton, Qi Xiang | 2005-03-15 |