Issued Patents All Time
Showing 25 most recent of 205 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12096703 | Semiconductor device and manufacturing method of semiconductor device | Taiwei CHIU, Tingying SHEN | 2024-09-17 |
| 10707138 | High yield package assembly technique | Shiying Xiong, Thao H. T. Vo, Felino E. Pagaduan, Xiao-Yu Li, Glenn O'Rourke | 2020-07-07 |
| 9496268 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2016-11-15 |
| 9460924 | Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system | Witold P. Maszara | 2016-10-04 |
| 9461161 | Memory element circuitry with minimum oxide definition width | Jun Liu | 2016-10-04 |
| 9214433 | Charge damage protection on an interposer for a stacked die assembly | Xiao-Yu Li, Cinti X. Chen, Glenn O'Rourke | 2015-12-15 |
| 9196749 | Programmable device with a metal oxide semiconductor field effect transistor | Charu Sardana, Albert Ratnakumar, Bradley Jensen | 2015-11-24 |
| 9190332 | Method of fabricating integrated circuit transistors with multipart gate conductors | Jun Liu, Albert Ratnakumar, Jeffrey Tung | 2015-11-17 |
| 9165640 | Method of using a PMOS pass gate | Jun Liu, Albert Ratnakumar, Irfan Rahim | 2015-10-20 |
| 8966423 | Integrating optimal planar and three-dimensional semiconductor design layouts | Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Jongwook Kye | 2015-02-24 |
| 8904324 | Parameterized cell for planar and finFET technology design | Navneet Jain, Paul D. Mesa, Qinglei Wang, Mahbub Rashed | 2014-12-02 |
| 8804407 | PMOS pass gate | Jun Liu, Albert Ratnakumar, Irfan Rahim | 2014-08-12 |
| 8750026 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2014-06-10 |
| 8735983 | Integrated circuit transistors with multipart gate conductors | Jun Liu, Albert Ratnakumar, Jeffrey Tung | 2014-05-27 |
| 8735050 | Integrated circuits and methods for fabricating integrated circuits using double patterning processes | Lei Yuan, Hidekazu Yoshida, Jongwook Kye, Mahbub Rashed | 2014-05-27 |
| 8649209 | Memory element circuitry with reduced oxide definition width | Jun Liu | 2014-02-11 |
| 8633731 | Programmable integrated circuit with thin-oxide passgates | Irfan Rahim, Mao Du, Jeffrey Tung, Jun Liu | 2014-01-21 |
| 8530976 | Memory element transistors with reversed-workfunction gate conductors | Albert Ratnakumar, Jun Liu | 2013-09-10 |
| 8502283 | Strained fully depleted silicon on insulator semiconductor device | Niraj Subba, Witold P. Maszara, Zoran Krivokapic, Ming-Ren Lin | 2013-08-06 |
| 8482963 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung +5 more | 2013-07-09 |
| 8264214 | Very low voltage reference circuit | Albert Ratnakumar, Simardeep Maangat, Jun Liu | 2012-09-11 |
| 8242581 | Mixed-gate metal-oxide-semiconductor varactors | Albert Ratnakumar, Wilson Wong, Jun Liu, Jeffrey Tung | 2012-08-14 |
| 8218353 | Memory element circuitry with stressed transistors | Jun Liu, Shankar Sinha, Yow-Juang Liu | 2012-07-10 |
| 8138791 | Stressed transistors with reduced leakage | Albert Ratnakumar, Jun Liu, Jeffrey Tung | 2012-03-20 |
| 8081502 | Memory elements with body bias control | Irfan Rahim, Jun Liu, Andy L. Lee, William Bradley Vest, Lu Zhou +3 more | 2011-12-20 |