Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9984734 | Programmable integrated circuits with in-operation reconfiguration capability | Andy L. Lee, Ning Cheng | 2018-05-29 |
| 9607671 | Programmable integrated circuits with in-operation reconfiguration capability | Andy L. Lee, Ning Cheng | 2017-03-28 |
| 9576617 | Multiport memory element circuitry | Shih-Lin Lee, Peter J. McElheny, Preminder Singh | 2017-02-21 |
| 9496268 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shih-Lin Lee, Jeffrey Tung, Albert Ratnakumar +5 more | 2016-11-15 |
| 9401200 | Memory cells with p-type diffusion read-only port | Mark T. Chan | 2016-07-26 |
| 9318333 | Dielectric extension to mitigate short channel effects | Vidyut Gopal, Jean Y. Yang, Phillip Jones | 2016-04-19 |
| 9299396 | Programmable integrated circuits with in-operation reconfiguration capability | Andy L. Lee, Ning Cheng | 2016-03-29 |
| 9276083 | Memory elements with stacked pull-up devices | Brian Wong, Shih-Lin Lee, Wei Zhang, Abhishek SHARMA | 2016-03-01 |
| 9171936 | Barrier region underlying source/drain regions for dual-bit memory devices | Yi He, Zhizheng Liu, Ming Sang Kwan | 2015-10-27 |
| 9111641 | Memory circuit including memory devices, a freeze circuit and a test switch | Rakesh Patel | 2015-08-18 |
| 9006794 | Low-voltage programmable electrical fuses | Shuang Xie, Cheng-Hsiung Huang | 2015-04-14 |
| 8995177 | Integrated circuits with asymmetric transistors | Shih-Lin Lee, Peter J. McElheny | 2015-03-31 |
| 8861283 | Systems and methods for reducing leakage current in memory arrays | Brian Wong, Shih-Lin Lee, Abhishek SHARMA | 2014-10-14 |
| 8755218 | Multiport memory element circuitry | Shih-Lin Lee, Peter J. McElheny, Preminder Singh | 2014-06-17 |
| 8750026 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shih-Lin Lee, Jeffrey Tung, Albert Ratnakumar +5 more | 2014-06-10 |
| 8638594 | Integrated circuits with asymmetric transistors | Shih-Lin Lee, Peter J. McElheny | 2014-01-28 |
| 8619464 | Static random-access memory having read circuitry with capacitive storage | Brian Wong, Shih-Lin Lee, Abhishek SHARMA | 2013-12-31 |
| 8599598 | 3T device based memory circuits and arrays | Rakesh Patel | 2013-12-03 |
| 8482963 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Yanzhong Xu, Shih-Lin Lee, Jeffrey Tung, Albert Ratnakumar +5 more | 2013-07-09 |
| 8409952 | Method of forming an electronic device including forming a charge storage element in a trench of a workpiece | Suketu Arun Parikh, Olov Karlsson, Yun-Ju Sun, Timothy Thurgate | 2013-04-02 |
| 8218353 | Memory element circuitry with stressed transistors | Jun Liu, Qi Xiang, Yow-Juang Liu | 2012-07-10 |
| 8148770 | Memory device with buried bit line structure | Timothy Thurgate | 2012-04-03 |
| 8130559 | MEMS switching device and conductive bridge device based circuits | Rakesh Patel | 2012-03-06 |
| 7888218 | Using thick spacer for bitline implant then remove | Zhizheng Liu, Timothy Thurgate, Ming Sang Kwan | 2011-02-15 |
| 7678674 | Memory cell dual pocket implant | Ashot Melik-Martirosian, Ihsan Djomehri | 2010-03-16 |