| 11257675 |
Tilted implant for poly resistors |
Shenqing Fang, Kuo-Tung Chang |
2022-02-22 |
|
| 10644016 |
Charge-trapping memory device |
Kuo-Tung Chang, Shenqing Fang |
2020-05-05 |
|
| 9559216 |
Semiconductor memory device and method for biasing same |
Srinivasa Banna, Michael A. Van Buskirk |
2017-01-31 |
$12,992,000 |
| 9524971 |
Techniques for providing a semiconductor memory device |
Srinivasa Banna, Michael A. Van Buskirk |
2016-12-20 |
|
| 9263133 |
Techniques for providing a semiconductor memory device |
Srinivasa Banna, Michael A. Van Bushkirk |
2016-02-16 |
$6,293,000 |
| 9019759 |
Techniques for providing a semiconductor memory device |
Srinivasa Banna, Michael A. Van Buskirk |
2015-04-28 |
$18,309,000 |
| 8547738 |
Techniques for providing a semiconductor memory device |
Srinivasa Banna, Michael A. Van Buskirk |
2013-10-01 |
$5,978,000 |
| 8531878 |
Techniques for providing a semiconductor memory device |
Srinivasa Banna, Michael A. Van Buskirk |
2013-09-10 |
$5,150,000 |
| 8415734 |
Memory device protection layer |
Rinji Sugino, Jean Y. Yang, Michael Brennan |
2013-04-09 |
$2,664,000 |
| 8409952 |
Method of forming an electronic device including forming a charge storage element in a trench of a workpiece |
Suketu Arun Parikh, Olov Karlsson, Yun-Ju Sun, Shankar Sinha |
2013-04-02 |
$2,639,000 |
| 8208296 |
Apparatus and method for extended nitride layer in a flash memory |
Shenqing Fang, Kuo-Tung Chang, Youseok Suh |
2012-06-26 |
$3,209,000 |
| 8148770 |
Memory device with buried bit line structure |
Shankar Sinha |
2012-04-03 |
$3,391,000 |
| 8076712 |
Semiconductor memory comprising dual charge storage nodes and methods for its fabrication |
Chungho Lee, Ashot Melik-Martirosian, Wei Zheng, Chi Chang, Hiroyuki Kinoshita +2 more |
2011-12-13 |
$655,000 |
| 7952938 |
Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory |
Gulzar Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Kuo-Tung Chang +2 more |
2011-05-31 |
$2,196,000 |
| 7888218 |
Using thick spacer for bitline implant then remove |
Zhizheng Liu, Shankar Sinha, Ming Sang Kwan |
2011-02-15 |
$2,637,000 |
| 7785965 |
Dual storage node memory devices and methods for fabricating the same |
Unsoon Kim, Kyunghoon Min, Ning Cheng, Hiroyuki Kinoshita, Sugino Rinji +3 more |
2010-08-31 |
$1,139,000 |
| 7767517 |
Semiconductor memory comprising dual charge storage nodes and methods for its fabrication |
Chungho Lee, Ashot Melik-Martirosian, Wei Zheng, Chi Chang, Hiroyuki Kinoshita +2 more |
2010-08-03 |
$3,923,000 |
| 7746705 |
Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory |
Gulzar Ahmed Kathawala, Wei Zheng, Zhizheng Liu, Sung-Yong Chung, Kuo-Tung Chang +2 more |
2010-06-29 |
$497,000 |
| 7696038 |
Methods for fabricating flash memory devices |
Ning Cheng, Kuo-Tung Chang, Hiroyuki Kinoshita, Wei Zheng, Ashot Melik-Martirosian +2 more |
2010-04-13 |
|
| 7671405 |
Deep bitline implant to avoid program disturb |
Yi He, Ming Sang Kwan, Zhizheng Liu, Xuguang Wang |
2010-03-02 |
|
| 7626869 |
Multi-phase wordline erasing for flash memory |
Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene Hamilton +4 more |
2009-12-01 |
|
| 7489560 |
Reduction of leakage current and program disturbs in flash memory devices |
Kuo-Tung Chang |
2009-02-10 |
$91,000 |
| 7462907 |
Method of increasing erase speed in memory arrays |
Ashot Melik-Martirosian |
2008-12-09 |
$299,000 |
| 7301193 |
Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell |
Shenqing Fang, Kuo-Tung Chang, Richard Fastow, Angela T. Hui, Kazuhiro Mizutani +4 more |
2007-11-27 |
$6,734,000 |
| 7125763 |
Silicided buried bitline process for a non-volatile memory cell |
Daniel Sobek, Mark Randolph |
2006-10-24 |
$7,024,000 |
