Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7067381 | Structure and method to reduce drain induced barrier lowering | Nga-Ching Wong | 2006-06-27 |
| 7049188 | Lateral doped channel | Nga-Ching Wong, Sameer Haddad | 2006-05-23 |
| 7009271 | Memory device with an alternating Vss interconnection | Richard Fastow | 2006-03-07 |
| 6963106 | Memory array with memory cells having reduced short channel effects | Richard Fastow, Yue-Song He, Kazuhiro Mizutani | 2005-11-08 |
| 6911704 | Memory cell array with staggered local inter-connect structure | Mark Randolph, Sameer Haddad, Richard Fastow | 2005-06-28 |
| 6908816 | Method for forming a dielectric spacer in a non-volatile memory device | Nga-Ching Wong | 2005-06-21 |
| 6773990 | Method for reducing short channel effects in memory cells and related structure | Richard Fastow, Yue-Song He, Kazuhiro Mizutani | 2004-08-10 |
| 6770938 | Diode fabrication for ESD/EOS protection | Michael Fliesler, Mark T. Ramsbey, Mark Randolph, Ian Morgan, Paohua Kuo +1 more | 2004-08-03 |
| 6653189 | Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory | Sameer Haddad, Yue-Song He, Chi Chang, Mark Randolph, Ngaching Wong | 2003-11-25 |
| 6524914 | Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory | Yue-Song He, Sameer Haddad, Chi Chang | 2003-02-25 |
| 6518072 | Deposited screen oxide for reducing gate edge lifting | Carl Robert Huster, Daniel Sobek, Sameer Haddad | 2003-02-11 |
| 6487121 | Method of programming a non-volatile memory cell using a vertical electric field | Carl Robert Huster | 2002-11-26 |
| 6456536 | Method of programming a non-volatile memory cell using a substrate bias | Daniel Sobek, Janet Wang, Narbeh Derhacobian | 2002-09-24 |
| 6417081 | Process for reduction of capacitance of a bitline for a non-volatile memory cell | — | 2002-07-09 |
| 6410956 | Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices | Vei-Han Chan, Scott Luning, Mark Randolph, Nicholas H. Tripsas, Daniel Sobek +2 more | 2002-06-25 |
| 6387755 | Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting | Scott Luning | 2002-05-14 |
| 6366501 | Selective erasure of a non-volatile memory cell of a flash memory device | Daniel Sobek | 2002-04-02 |
| 6349062 | Selective erasure of a non-volatile memory cell of a flash memory device | — | 2002-02-19 |
| 6337246 | Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing | Daniel Sobek, Carl Robert Huster, Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2002-01-08 |
| 6329257 | Method for laterally peaked source doping profiles for better erase control in flash memory devices | Scott Luning, Daniel Sobek | 2001-12-11 |
| 6329273 | Solid-source doping for source/drain to eliminate implant damage | Carl Robert Huster | 2001-12-11 |
| 6329687 | Two bit flash cell with two floating gate regions | Daniel Sobek, Carl Robert Huster, Masaaki Higashitani | 2001-12-11 |
| 6268624 | Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing | Daniel Sobek, Carl Robert Huster, Tuan Pham, Mark T. Ramsbey, Sameer Haddad | 2001-07-31 |
| 6255165 | Nitride plug to reduce gate edge lifting | Carl Robert Huster, Daniel Sobek | 2001-07-03 |
| 6236596 | Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices | Daniel Sobek, Scott Luning, Vei-Han Chan, Sameer Haddad | 2001-05-22 |