| 7232729 |
Method for manufacturing a double bitline implant |
— |
2007-06-19 |
| 7208382 |
Semiconductor device with high conductivity region using shallow trench |
Jeffrey P. Erhardt, Kashmir Sahota, Emmanuil H. Lingunis |
2007-04-24 |
| 7176113 |
LDC implant for mirrorbit to improve Vt roll-off and form sharper junction |
Weidong Qian, Sameer Haddad, Mark Randolph, Mark T. Ramsbey, Tazrien Kamal |
2007-02-13 |
| 7151292 |
Dielectric memory cell structure with counter doped channel region |
— |
2006-12-19 |
| 7067381 |
Structure and method to reduce drain induced barrier lowering |
Timothy Thurgate |
2006-06-27 |
| 7049188 |
Lateral doped channel |
Timothy Thurgate, Sameer Haddad |
2006-05-23 |
| 7023740 |
Substrate bias for programming non-volatile memory |
Darlene Hamilton |
2006-04-04 |
| 7011998 |
High voltage transistor scaling tilt ion implant method |
Dong-Hyuk Ju |
2006-03-14 |
| 6958272 |
Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
Emmanuil H. Lingunis, Sameer Haddad, Mark Randolph, Mark T. Ramsbey, Ashot Melik-Martirosian +2 more |
2005-10-25 |
| 6908816 |
Method for forming a dielectric spacer in a non-volatile memory device |
Timothy Thurgate |
2005-06-21 |
| 6833297 |
Method for reducing drain induced barrier lowering in a memory device |
Richard Fastow, Yue-Song He |
2004-12-21 |
| 6475816 |
Method for measuring source and drain junction depth in silicon on insulator technology |
Concetta Riccobene, Tim Thurgate |
2002-11-05 |