Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Nga-Ching Wong — 12 Patents

AMD: 9 patents #1,376 of 9,280Top 15%
SLSpansion Llc.: 3 patents #241 of 769Top 35%
San Jose, CA: #5,425 of 32,062 inventorsTop 20%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Nga-Ching Wong has been granted 12 US patents while listed as an inventor at AMD. The first was granted in 2002 and the most recent in June 2007. Nga-Ching Wong ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Nga-Ching Wong in San Jose, CA, US.

Patents per Year

Patents granted per year, 2002 to 2007Bar chart with a peak of 5 patents in 2006.peak 52002: 1 patents20022004: 1 patents20042005: 2 patents20052006: 5 patents20062007: 3 patents2007

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7232729 Method for manufacturing a double bitline implant 2007-06-19 $7,720,000
7208382 Semiconductor device with high conductivity region using shallow trench Jeffrey P. Erhardt, Kashmir Sahota, Emmanuil H. Lingunis 2007-04-24 $10,633,000
7176113 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction Weidong Qian, Sameer Haddad, Mark Randolph, Mark T. Ramsbey, Tazrien Kamal 2007-02-13 $15,804,000
7151292 Dielectric memory cell structure with counter doped channel region 2006-12-19 $3,490,000
7067381 Structure and method to reduce drain induced barrier lowering Timothy Thurgate 2006-06-27 $11,248,000
7049188 Lateral doped channel Timothy Thurgate, Sameer Haddad 2006-05-23 $17,017,000
7023740 Substrate bias for programming non-volatile memory Darlene Hamilton 2006-04-04 $14,413,000
7011998 High voltage transistor scaling tilt ion implant method Dong-Hyuk Ju 2006-03-14 $17,128,000
6958272 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell Emmanuil H. Lingunis, Sameer Haddad, Mark Randolph, Mark T. Ramsbey, Ashot Melik-Martirosian +2 more 2005-10-25 $11,546,000
6908816 Method for forming a dielectric spacer in a non-volatile memory device Timothy Thurgate 2005-06-21 $19,558,000
6833297 Method for reducing drain induced barrier lowering in a memory device Richard Fastow, Yue-Song He 2004-12-21 $5,396,000
6475816 Method for measuring source and drain junction depth in silicon on insulator technology Concetta Riccobene, Tim Thurgate 2002-11-05 $1,578,000