Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Concetta Riccobene — 15 Patents

AMD: 15 patents #798 of 9,280Top 9%
Mountain View, CA: #1,460 of 11,022 inventorsTop 15%
California: #40,789 of 386,348 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Concetta Riccobene has been granted 15 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in July 2004. Concetta Riccobene ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Concetta Riccobene in Mountain View, CA, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6765227 Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding Bin Yu, William G. En, Judy Xilin An 2004-07-20 $1,607,000
6717212 Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure Dong-Hyuk Ju, William G. En, Srinath Krishnan, Zoran Krivokapic, Judy Xilin An +1 more 2004-04-06 $3,021,000
6667512 Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) Carl Robert Huster 2003-12-23 $5,236,000
6548335 Selective epitaxy to reduce gate/gate dielectric interface roughness Carl Robert Huster, Scott Luning 2003-04-15 $2,272,000
6538284 SOI device with body recombination region, and method Dong-Hyuk Ju 2003-03-25 $2,887,000
6525378 Raised S/D region for optimal silicidation to control floating body effects in SOI devices 2003-02-25 $1,843,000
6515333 Removal of heat from SOI device 2003-02-04 $1,030,000
6479868 Silicon-on-insulator transistors with asymmetric source/drain junctions formed by angled germanium implantation Xilin Judy An, Bin Yu 2002-11-12 $1,765,000
6475816 Method for measuring source and drain junction depth in silicon on insulator technology Nga-Ching Wong, Tim Thurgate 2002-11-05 $1,578,000
6410371 Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer Bin Yu, William G. En, Judy Xilin An 2002-06-25 $2,000,000
6396103 Optimized single side pocket implant location for a field effect transistor Carl Robert Huster 2002-05-28 $2,985,000
6391767 Dual silicide process to reduce gate resistance Carl Robert Huster, Wei Long 2002-05-21 $2,063,000
6274501 Formation of structure to accurately measure source/drain resistance Ognjen Milic-Strkalj 2001-08-14 $3,163,000
6242329 Method for manufacturing asymmetric channel transistor Carl Robert Huster, Richard P. Rouse, Donald L. Wollesen 2001-06-05 $7,807,000
6229184 Semiconductor device with a modulated gate oxide thickness 2001-05-08 $6,632,000