Issued Patents All Time
Showing 25 most recent of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10496291 | Maintaining data integrity during data migration | Narasimhan Badrinarayanan, Kannan Andireddi | 2019-12-03 |
| 8949083 | Modeling gate transconductance in a sub-circuit transistor model | Jia Feng, Zhi-Yuan Wu, Juhi Bansal | 2015-02-03 |
| 7768095 | Shallow trench isolation process utilizing differential liners | — | 2010-08-03 |
| 7626242 | Shallow trench isolation process utilizing differential liners | — | 2009-12-01 |
| 7364962 | Shallow trench isolation process utilizing differential liners | — | 2008-04-29 |
| 7253068 | Dual SOI film thickness for body resistance control | Dong-Hyuk Ju, Mario Pelella | 2007-08-07 |
| 7132683 | Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies | William G. En | 2006-11-07 |
| 7122863 | SOI device with structure for enhancing carrier recombination and method of fabricating same | Dong-Hyuk Ju, William G. En, Xilin Judy An | 2006-10-17 |
| 7071044 | Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS | William G. En | 2006-07-04 |
| 7045433 | Tip architecture with SPE for buffer and deep source/drain regions | — | 2006-05-16 |
| 6955969 | Method of growing as a channel region to reduce source/drain junction capacitance | Ihsan Djomehri, Jung-Suk Goo, Witold P. Maszara, James Pan, Qi Xiang | 2005-10-18 |
| 6830987 | Semiconductor device with a silicon-on-void structure and method of making the same | Mario Pelella, William G. En, Witold P. Maszara | 2004-12-14 |
| 6727149 | Method of making a hybrid SOI device that suppresses floating body effects | Witold P. Maszara, Zoran Krivokapic | 2004-04-27 |
| 6717212 | Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure | Dong-Hyuk Ju, William G. En, Concetta Riccobene, Zoran Krivokapic, Judy Xilin An +1 more | 2004-04-06 |
| 6713819 | SOI MOSFET having amorphized source drain and method of fabrication | William G. En, Dong-Hyuk Ju | 2004-03-30 |
| 6630376 | Body-tied-to-body SOI CMOS inverter circuit | Jerry G. Fossum, Meng-Hsueh Chiang | 2003-10-07 |
| 6613643 | Structure, and a method of realizing, for efficient heat removal on SOI | Matthew S. Buynoski | 2003-09-02 |
| 6611023 | Field effect transistor with self alligned double gate and method of forming same | William G. En | 2003-08-26 |
| 6589823 | Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug | Stephen G. Beebe, Zoran Krivokapic | 2003-07-08 |
| 6566213 | Method of fabricating multi-thickness silicide device formed by disposable spacers | William G. En, Dong-Hyuk Ju, Bin Yu | 2003-05-20 |
| 6548361 | SOI MOSFET and method of fabrication | William G. En, Dong-Hyuk Ju | 2003-04-15 |
| 6541821 | SOI device with source/drain extensions and adjacent shallow pockets | Witold P. Maszara, Zoran Krivokapic | 2003-04-01 |
| 6535015 | Device and method for testing performance of silicon structures | Dong-Hyuk Ju, William G. En, Siu Lun Lee, Richard K. Klein | 2003-03-18 |
| 6518631 | Multi-Thickness silicide device formed by succesive spacers | William G. En, Dong-Hyuk Ju, Bin Yu | 2003-02-11 |
| 6512244 | SOI device with structure for enhancing carrier recombination and method of fabricating same | Dong-Hyuk Ju, William G. En, Xilin Judy An | 2003-01-28 |