Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8818785 | Method and apparatus for simulating gate capacitance of a tucked transistor device | Ciby Thuruthiyil, Venkat Ramasubramanian, John Vincent Faricelli | 2014-08-26 |
| 8618592 | Dynamic random access memory (DRAM) cells and methods for fabricating the same | Hyun-Jin Cho, Sang Hoo Dhong, Gurupada Mandal | 2013-12-31 |
| 8586981 | Silicon-on-insulator (“SOI”) transistor test structure for measuring body-effect | Qiang Chen | 2013-11-19 |
| 8293606 | Body tie test structure for accurate body effect measurement | Sriram Madhavan, Qiang Chen, Darin A. Chan | 2012-10-23 |
| 8275596 | Method for robust statistical semiconductor device modeling | Vineet Wason, Zhi-Yuan Wu, Ciby Thuruthiyil | 2012-09-25 |
| 8099269 | Two-step simulation methodology for aging simulations | Rasit Onur Topaloglu | 2012-01-17 |
| 7977172 | Dynamic random access memory (DRAM) cells and methods for fabricating the same | Hyun-Jin Cho, Sang Hoo Dhong, Gurupada Mandal | 2011-07-12 |
| 7932103 | Integrated circuit system with MOS device | Niraj Subba | 2011-04-26 |
| 7923785 | Field effect transistor having increased carrier mobility | Qi Xiang, Boon Yong Ang | 2011-04-12 |
| 7880229 | Body tie test structure for accurate body effect measurement | Sriram Madhavan, Qiang Chen, Darin A. Chan | 2011-02-01 |
| 7761823 | Method for adjusting a transistor model for increased circuit simulation accuracy | Qiang Chen | 2010-07-20 |
| 7732336 | Shallow trench isolation process and structure with minimized strained silicon consumption | Qi Xiang, James Pan | 2010-06-08 |
| 7462549 | Shallow trench isolation process and structure with minimized strained silicon consumption | Qi Xiang, James Pan | 2008-12-09 |
| 7176531 | CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric | Qi Xiang, Huicai Zhong, Allison Holbrook, Joong S. Jeon, George Jonathan Kluth | 2007-02-13 |
| 7170084 | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication | Qi Xiang, Haihong Wang | 2007-01-30 |
| 7138302 | Method of fabricating an integrated circuit channel region | Qi Xiang, James Pan | 2006-11-21 |
| 7078299 | Formation of finFET using a sidewall epitaxial layer | Witold P. Maszara, James Pan, Qi Xiang | 2006-07-18 |
| 7033869 | Strained silicon semiconductor on insulator MOSFET | Qi Xiang, James Pan | 2006-04-25 |
| 7015078 | Silicon on insulator substrate having improved thermal conductivity and method of its formation | Qi Xiang, James Pan | 2006-03-21 |
| 7012007 | Strained silicon MOSFET having improved thermal conductivity and method for its fabrication | Qi Xiang, James Pan | 2006-03-14 |
| 6962857 | Shallow trench isolation process using oxide deposition and anneal | Minh Van Ngo, Ming-Ren Lin, Eric N. Paton, Haihong Wang, Qi Xiang | 2005-11-08 |
| 6955969 | Method of growing as a channel region to reduce source/drain junction capacitance | Ihsan Djomehri, Srinath Krishnan, Witold P. Maszara, James Pan, Qi Xiang | 2005-10-18 |
| 6943087 | Semiconductor on insulator MOSFET having strained silicon channel | Qi Xiang, James Pan, Ming-Ren Lin | 2005-09-13 |
| 6936516 | Replacement gate strained silicon finFET process | Qi Xiang, James Pan | 2005-08-30 |
| 6929992 | Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift | Ihsan Djomehri, Qi Xiang, James Pan | 2005-08-16 |