Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8863057 | Method for selectively modeling narrow-width stacked device performance | Kaveri Mathur, Sriraaman Sridharan | 2014-10-14 |
| 8818785 | Method and apparatus for simulating gate capacitance of a tucked transistor device | Jung-Suk Goo, Venkat Ramasubramanian, John Vincent Faricelli | 2014-08-26 |
| 8309951 | Test structure for determining gate-to-body tunneling current in a floating body FET | Sushant S. Suryagandh | 2012-11-13 |
| 8275596 | Method for robust statistical semiconductor device modeling | Vineet Wason, Jung-Suk Goo, Zhi-Yuan Wu | 2012-09-25 |
| 8064832 | Method and test system for determining gate-to-body current in a floating body FET | Sushant S. Suryagandh | 2011-11-22 |
| 7844927 | Method for quality assured semiconductor device modeling | Zhi-Yuan Wu, Ali Icel, Judy Xilin An | 2010-11-30 |
| 6849469 | Monitor and control of silicidation using fourier transform infrared scatterometry | Bhanwar Singh, Ramkumar Subramanian | 2005-02-01 |
| 6756255 | CMOS process with an integrated, high performance, silicide agglomeration fuse | Philip A. Fisher | 2004-06-29 |