Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7943980 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications | Shenqing Fang, Kuo-Tung Chang, Tim Thurgate, Youseok Suh | 2011-05-17 |
| 7906395 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenqing Fang, Kuo-Tung Chang, Tim Thurgate, Youseok Suh | 2011-03-15 |
| 7803680 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenging Fang, Kuo-Tung Chang, Tim Thurgate, Youseok Suh | 2010-09-28 |
| 7675104 | Integrated circuit memory system employing silicon rich layers | Amol Joshi, Harpreet Sachar, Youseok Suh, Shenqing Fang, Chih-Yuh Yang +6 more | 2010-03-09 |
| 7498222 | Enhanced etching of a high dielectric constant layer | John Foster, Scott A. Bell, Simon S. Chan, Phillip Jones | 2009-03-03 |
| 7465644 | Isolation region bird's beak suppression | Simon S. Chan, Weidong Qian, Scott A. Bell, Phillip Jones | 2008-12-16 |
| 7176531 | CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric | Qi Xiang, Huicai Zhong, Jung-Suk Goo, Joong S. Jeon, George Jonathan Kluth | 2007-02-13 |
| 6975014 | Method for making an ultra thin FDSOI device with improved short-channel performance | Zoran Krivokapic, Sunny Cherian | 2005-12-13 |
| 6872613 | Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure | Qi Xiang, Huicai Zhong, Jung-Suk Goo, Joong S. Jeon, George Jonathan Kluth | 2005-03-29 |
| 6821713 | Method for lateral trimming of spacers | Jiahua Huang, Sunny Cherian | 2004-11-23 |
| 6709924 | Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate | Allen S. Yu, Jeffrey A. Shields | 2004-03-23 |
| 6605843 | Fully depleted SOI device with tungsten damascene contacts and method of forming same | Zoran Krivokapic, Sunny Cherian, Kai Yang | 2003-08-12 |
| 6495853 | Self-aligned gate semiconductor | Jiahua Huang, Sunny Cherian | 2002-12-17 |
| 6472326 | Reliable particle removal following a process chamber wet clean | Greg A. Johnson, Darlene Smith, Omar Serna, Theodros W. Mariam | 2002-10-29 |
| 6448163 | Method for fabricating T-shaped transistor gate | Sunny Cherian, Zoran Krivokapic | 2002-09-10 |
| 6383945 | High selectivity pad etch for thick topside stacks | Jiahua Huang, Jeffrey A. Shields | 2002-05-07 |
| 6358760 | Method for amorphous silicon local interconnect etch | Jiahua Huang, James Chiang, Sunny Cherian | 2002-03-19 |
| 6358362 | Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process | William G. En, Fei Wang | 2002-03-19 |
| 6060328 | Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process | William G. En, Fei Wang | 2000-05-09 |
| 6013156 | Bubble monitor for semiconductor manufacturing | Jiahua Huang, Aaron Fernandes | 2000-01-11 |
| 5920796 | In-situ etch of BARC layer during formation of local interconnects | Fei Wang, James Kai | 1999-07-06 |