| 7456062 |
Method of forming a semiconductor device |
Thorsten Kammler, Eric N. Paton, Paul R. Besser, Simon S. Chan |
2008-11-25 |
$3,883,000 |
| 7402485 |
Method of forming a semiconductor device |
Thorsten Kammler, Eric N. Paton, Scott Luning |
2008-07-22 |
$4,320,000 |
| 7402207 |
Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
Paul R. Besser, Eric N. Paton |
2008-07-22 |
$4,320,000 |
| 7378330 |
Cleaving process to fabricate multilayered substrates using low implantation doses |
Francois J. Henley, Michael A. Bryan |
2008-05-27 |
|
| 7298012 |
Shallow junction semiconductor |
Mario M. Pelella, Eric N. Paton, Witold P. Maszara |
2007-11-20 |
$5,989,000 |
| 7241700 |
Methods for post offset spacer clean for improved selective epitaxy silicon growth |
Eric N. Paton, Scott Luning |
2007-07-10 |
$17,592,000 |
| 7211473 |
Method and structure for controlling floating body effects |
Mario M. Pelella, Ping-Chin Yeh |
2007-05-01 |
$26,379,000 |
| 7132683 |
Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies |
Srinath Krishnan |
2006-11-07 |
$14,140,000 |
| 7122863 |
SOI device with structure for enhancing carrier recombination and method of fabricating same |
Dong-Hyuk Ju, Srinath Krishnan, Xilin Judy An |
2006-10-17 |
$21,769,000 |
| 7071044 |
Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS |
Srinath Krishnan |
2006-07-04 |
|
| 7056808 |
Cleaving process to fabricate multilayered substrates using low implantation doses |
Francois J. Henley, Michael A. Bryan |
2006-06-06 |
|
| 7033916 |
Shallow junction semiconductor and method for the fabrication thereof |
Mario M. Pelella, Eric N. Paton, Witold P. Maszara |
2006-04-25 |
$9,950,000 |
| 6964875 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance |
Mark W. Michael, Hai Hong Wang, Simon S. Chan |
2005-11-15 |
$25,400,000 |
| 6933579 |
Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby |
Witold P. Maszara, Mario M. Pelella |
2005-08-23 |
$8,041,000 |
| 6905971 |
Treatment of dielectric material to enhance etch rate |
Cyrus E. Tabery, Chih-Yuh Yang, Joong S. Jeon, Minh Van Ngo, Ming-Ren Lin |
2005-06-14 |
$5,811,000 |
| 6867130 |
Enhanced silicidation of polysilicon gate electrodes |
Olov Karlsson, Simon S. Chan, Mark W. Michael |
2005-03-15 |
$4,259,000 |
| 6841832 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance |
Mark W. Michael, Hai Hong Wang, Simon S. Chan |
2005-01-11 |
$4,696,000 |
| 6830987 |
Semiconductor device with a silicon-on-void structure and method of making the same |
Mario Pelella, Srinath Krishnan, Witold P. Maszara |
2004-12-14 |
$6,995,000 |
| 6812550 |
Wafer pattern variation of integrated circuit fabrication |
Eric N. Paton, Mario M. Pelella, Witold P. Maszara |
2004-11-02 |
$2,431,000 |
| 6780776 |
Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer |
Wen-Jie Qi, John G. Pellerin, Mark W. Michael, Darin A. Chan |
2004-08-24 |
$2,825,000 |
| 6764966 |
Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric |
Arvind Halliyal, Ming-Ren Lin, Minh Van Ngo, Chih-Yuh Yang |
2004-07-20 |
$1,607,000 |
| 6764917 |
SOI device with different silicon thicknesses |
Darin A. Chan, John G. Pellerin, Mark W. Michael |
2004-07-20 |
$1,607,000 |
| 6764898 |
Implantation into high-K dielectric material after gate etch to facilitate removal |
Joong S. Jeon, Minh Van Ngo, Ming-Ren Lin |
2004-07-20 |
$1,607,000 |
| 6765227 |
Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding |
Bin Yu, Judy Xilin An, Concetta Riccobene |
2004-07-20 |
$1,607,000 |
| 6723666 |
Method for reducing gate oxide surface irregularities |
Philip A. Fisher |
2004-04-20 |
$2,632,000 |
