| 8687417 |
Electronic device and method of biasing |
Ruigang Li, Jingrong Zhou, David Wu, Zhonghai Shi, James F. Buller +2 more |
2014-04-01 |
$6,826,000 |
| 8329519 |
Methods for fabricating a semiconductor device having decreased contact resistance |
Zhonghai Shi, David Wu |
2012-12-11 |
$1,376,000 |
| 8134208 |
Semiconductor device having decreased contact resistance |
Zhonghai Shi, David Wu |
2012-03-13 |
$9,355,000 |
| 7861195 |
Process for design of semiconductor circuits |
Darin A. Chan, Yi Zou, Yuansheng Ma, Marilyn I. Wright |
2010-12-28 |
$4,143,000 |
| 7793240 |
Compensating for layout dimension effects in semiconductor device modeling |
Akif Sultan, Jian Chen, Jingrong Zhou |
2010-09-07 |
$6,542,000 |
| 7761838 |
Method for fabricating a semiconductor device having an extended stress liner |
Zhonghai Shi, David Wu, James F. Buller, Jingrong Zhou, Akif Sultan |
2010-07-20 |
$12,141,000 |
| 7670938 |
Methods of forming contact openings |
David Wu |
2010-03-02 |
$5,781,000 |
| 7638837 |
Stress enhanced semiconductor device and methods for fabricating same |
Akif Sultan, David Wu |
2009-12-29 |
$14,633,000 |
| 7598161 |
Method of forming transistor devices with different threshold voltages using halo implant shadowing |
Jingrong Zhou, David Wu, James F. Buller, Akif Sultan |
2009-10-06 |
$63,123,000 |
| 7504270 |
Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same |
David Wu, Akif Sultan, Jingrong Zhou |
2009-03-17 |
$2,427,000 |
| 7473623 |
Providing stress uniformity in a semiconductor device |
Jian Chen |
2009-01-06 |
$9,608,000 |
| 7391226 |
Contact resistance test structure and methods of using same |
Raymond George Stephany |
2008-06-24 |
$20,105,000 |
| 7355201 |
Test structure for measuring electrical and dimensional characteristics |
Jianhong Zhu, David Wu |
2008-04-08 |
$4,787,000 |
| 7271047 |
Test structure and method for measuring the resistance of line-end vias |
Jianhong Zhu, David Wu |
2007-09-18 |
$10,707,000 |
| 6964875 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance |
William G. En, Hai Hong Wang, Simon S. Chan |
2005-11-15 |
$25,400,000 |
| 6867130 |
Enhanced silicidation of polysilicon gate electrodes |
Olov Karlsson, Simon S. Chan, William G. En |
2005-03-15 |
$4,259,000 |
| 6841832 |
Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance |
William G. En, Hai Hong Wang, Simon S. Chan |
2005-01-11 |
$4,696,000 |
| 6780776 |
Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer |
Wen-Jie Qi, John G. Pellerin, William G. En, Darin A. Chan |
2004-08-24 |
$2,825,000 |
| 6764917 |
SOI device with different silicon thicknesses |
Darin A. Chan, William G. En, John G. Pellerin |
2004-07-20 |
$1,607,000 |
| 6713357 |
Method to reduce parasitic capacitance of MOS transistors |
Hai Hong Wang, Wen-Jie Qi, William G. En, John G. Pellerin |
2004-03-30 |
$4,272,000 |
| 6661057 |
Tri-level segmented control transistor and fabrication method |
Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Bradley T. Moore +1 more |
2003-12-09 |
|
| 6566696 |
Self-aligned VT implant |
Jon D. Cheek, Derick J. Wristers, James F. Buller |
2003-05-20 |
$2,116,000 |
| 6552776 |
Photolithographic system including light filter that compensates for lens error |
Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more |
2003-04-22 |
$3,266,000 |
| 6410409 |
Implanted barrier layer for retarding upward diffusion of substrate dopant |
Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more |
2002-06-25 |
$2,000,000 |
| 6380055 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer |
Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Bradley T. Moore +1 more |
2002-04-30 |
$1,930,000 |
