Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10865980 | Configurable security light | Scott Blaise Tylicki, Apollo Paul Paredes, Kenneth Earl Ramsey, Amer Salihovic, Leeman Elliot Stevens | 2020-12-15 |
| 9905976 | Mounting strap having a connector to connect an electric fixture to a junction box | Timothy Gale Birdwell, Eric Bretschneider, James J. Fitzgibbon, Scott Blaise Tylicki | 2018-02-27 |
| 9595794 | Electrical fixture secured to a junction box via a cover plate having an electrical connector | Timothy Gale Birdwell, Eric Bretschneider, James J. Fitzgibbon, Scott Blaise Tylicki | 2017-03-14 |
| 9172199 | Electrical fixture secured to a junction box via a cover plate having an electrical connector | Timothy Gale Birdwell, Eric Bretschneider, James J. Fitzgibbon, Scott Blaise Tylicki | 2015-10-27 |
| 6689668 | Methods to improve density and uniformity of hemispherical grain silicon layers | Mohamed el-Hamdi, Tony Phan, Luther Hendrix | 2004-02-10 |
| 6661057 | Tri-level segmented control transistor and fabrication method | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2003-12-09 |
| 6552776 | Photolithographic system including light filter that compensates for lens error | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2003-04-22 |
| 6410409 | Implanted barrier layer for retarding upward diffusion of substrate dopant | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2002-06-25 |
| 6380055 | Dopant diffusion-retarding barrier region formed within polysilicon gate layer | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2002-04-30 |
| 6372588 | Method of making an IGFET using solid phase diffusion to dope the gate, source and drain | Derick J. Wristers, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2002-04-16 |
| 6259142 | Multiple split gate semiconductor device and fabrication method | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2001-07-10 |
| 6225151 | Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Daniel Kadosh +2 more | 2001-05-01 |
| 6201278 | Trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2001-03-13 |
| 6197645 | Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2001-03-06 |
| 6188114 | Method of forming an insulated-gate field-effect transistor with metal spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2001-02-13 |
| 6166354 | System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more | 2000-12-26 |
| 6146978 | Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance | Mark W. Michael, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause +1 more | 2000-11-14 |
| 6111260 | Method and apparatus for in situ anneal during ion implant | Robert Dawson, H. Jim Fulford, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2000-08-29 |
| 6100146 | Method of forming trench transistor with insulative spacers | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2000-08-08 |
| 6096639 | Method of forming a local interconnect by conductive layer patterning | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2000-08-01 |
| 6087706 | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls | Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Mark W. Michael +1 more | 2000-07-11 |
| 6080629 | Ion implantation into a gate electrode layer using an implant profile displacement layer | Mark I. Gardner, Robert Dawson, H. Jim Fulford, Frederick N. Hause, Mark W. Michael +1 more | 2000-06-27 |
| 6060345 | Method of making NMOS and PMOS devices with reduced masking steps | Frederick N. Hause, Robert Dawson, H. Jim Fulford, Mark I. Gardner, Mark W. Michael +1 more | 2000-05-09 |
| 6048785 | Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching | H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2000-04-11 |
| 6030752 | Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device | H. Jim Fulford, Robert Dawson, Mark I. Gardner, Frederick N. Hause, Mark W. Michael +1 more | 2000-02-29 |