Issued Patents All Time
Showing 1–25 of 359 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12408321 | 3D horizontal memory cell with sequential 3D vertical stacking | Mark I. Gardner, Partha Mukhopadhyay | 2025-09-02 |
| 12381118 | 3D multiple location compressing bonded arm for advanced integration | Andrew WELOTH, Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, Anton J. deVilliers +1 more | 2025-08-05 |
| 12363956 | 2D material to integrate 3D horizontal nanosheets using a carrier nanosheet | Mark I. Gardner | 2025-07-15 |
| 12356706 | Methods for forming high performance three dimensionally stacked transistors based on dielectric nano sheets | Mark I. Gardner | 2025-07-08 |
| 12349424 | Epitaxial semiconductor 3D horizontal nano sheet with high mobility 2D material channel | Mark I. Gardner, Partha Mukhopadhyay | 2025-07-01 |
| 12342568 | 3D device with a plurality of core wiring layout architecture | Mark I. Gardner | 2025-06-24 |
| 12342603 | Plurality of devices in adjacent 3D stacks in different circuit locations | Mark I. Gardner | 2025-06-24 |
| 12336270 | High performance new channel materials precision aligned 3D CFET device architecture | Mark I. Gardner | 2025-06-17 |
| 12328919 | 3D isolation of a segmentated 3D nanosheet channel region | Mark I. Gardner | 2025-06-10 |
| 12324206 | Semiconductor devices and methods of manufacturing thereof | Mark I. Gardner, Partha Mukhopadhyay | 2025-06-03 |
| 12317577 | 3D semiconductor device with 2D semiconductor material and method of forming the same | Mark I. Gardner | 2025-05-27 |
| 12317481 | 3D memory with cell stacking using an in-situ capacitor stack | Mark I. Gardner | 2025-05-27 |
| 12302606 | Semiconductor devices with crystallized channel regions and methods of manufacturing thereof | Mark I. Gardner | 2025-05-13 |
| 12288747 | Multi-dimensional metal first device layout and circuit design | Mark I. Gardner, Partha Mukhopadhyay | 2025-04-29 |
| 12289885 | 3D integration of 3D NAND and vertical logic beneath memory | Mark I. Gardner | 2025-04-29 |
| 12272692 | 3D selective material transformation to integrate 2D material elements | Mark I. Gardner | 2025-04-08 |
| 12261209 | Replacement channel 2D material integration | Robert D. Clark, Mark I. Gardner | 2025-03-25 |
| 12249659 | 2D materials with inverted gate electrode for high density 3D stacking | Mark I. Gardner | 2025-03-11 |
| 12243920 | Method to form selective high-k deposition on 2D materials | Mark I. Gardner | 2025-03-04 |
| 12218011 | Method of making 3D segmented devices for enhanced 3D circuit density | Mark I. Gardner | 2025-02-04 |
| 12218195 | Vertical semiconductor device in narrow slots within trench | Mark I. Gardner | 2025-02-04 |
| 12218244 | Vertical transistor structures and methods utilizing selective formation | Mark I. Gardner, Partha Mukhopadhyay | 2025-02-04 |
| 12191210 | Formation of high density 3D circuits with enhanced 3D conductivity | Mark I. Gardner, Partha Mukhopadhyay | 2025-01-07 |
| 12176249 | 3D nano sheet method using 2D material integrated with conductive oxide for high performance devices | Mark I. Gardner, Partha Mukhopadhyay | 2024-12-24 |
| 12170326 | Three-dimensional device with vertical core and bundled wiring | Mark I. Gardner | 2024-12-17 |