Issued Patents All Time
Showing 25 most recent of 199 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381118 | 3D multiple location compressing bonded arm for advanced integration | Andrew WELOTH, Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford +1 more | 2025-08-05 |
| 12381093 | Hybrid patterning-bonding semiconductor tool | Anthony R. Schepis, Andrew WELOTH, David Conklin | 2025-08-05 |
| 12374562 | Wafer shape control for W2W bonding | Anthony R. Schepis, Andrew WELOTH, David Conklin | 2025-07-29 |
| 12354991 | Replacement buried power rail in backside power delivery | Hoyoung Kang, Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2025-07-08 |
| 12336274 | Self-aligned method for vertical recess for 3D device integration | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Subhadeep Kal +1 more | 2025-06-17 |
| 12327726 | Wet-dry bilayer resist dual tone exposure | — | 2025-06-10 |
| 12276922 | Backside deposition tuning of stress to control wafer bow in semiconductor processing | Daniel Fulford | 2025-04-15 |
| 12249508 | Selective patterning with wet-dry bilayer resist | — | 2025-03-11 |
| 12099299 | Method of patterning a substrate using a sidewall spacer etch mask | Jodi Grzeskowiak, Anthony R. Schepis | 2024-09-24 |
| 12040271 | Power delivery network for CFET with buried power rails | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2024-07-16 |
| 12020990 | Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks | Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner +1 more | 2024-06-25 |
| 12014984 | Method of manufacturing a semiconductor apparatus having stacked devices | Lars Liebmann, Jeffrey Smith | 2024-06-18 |
| 12001147 | Precision multi-axis photolithography alignment correction using stressor film | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford | 2024-06-04 |
| 11990334 | Method for tuning stress transitions of films on a substrate | Daniel Fulford, Jodi Grzeskowiak | 2024-05-21 |
| 11966171 | Method for producing overlay results with absolute reference for semiconductor manufacturing | — | 2024-04-23 |
| 11901360 | Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Jeffrey Smith, Kandabara Tapily | 2024-02-13 |
| 11883837 | System and method for liquid dispense and coverage control | Mirko Vukovic, Daniel Fulford | 2024-01-30 |
| 11862497 | Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking | H. Jim Fulford, Anthony R. Schepis | 2024-01-02 |
| 11854806 | Method for pattern reduction using a staircase spacer | Daniel Fulford | 2023-12-26 |
| 11848236 | Method for recessing a fill material within openings formed on a patterned substrate | Michael Murphy | 2023-12-19 |
| 11841617 | Method of forming a narrow trench | Jodi Grzeskowiak, Daniel Fulford, Richard A. Farrell, Jeffrey Smith | 2023-12-12 |
| 11810854 | Multi-dimensional vertical switching connections for connecting circuit elements | Mark I. Gardner, H. Jim Fulford | 2023-11-07 |
| 11782346 | Method of patterning a substrate using a sidewall spacer etch mask | Jodi Grzeskowiak, Anthony R. Schepis | 2023-10-10 |
| 11776808 | Planarization of spin-on films | Anthony R. Schepis | 2023-10-03 |
| 11776812 | Method for pattern reduction using a staircase spacer | Daniel Fulford | 2023-10-03 |