Issued Patents All Time
Showing 26–50 of 199 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Paul Gutwin, Robert D. Clark | 2023-09-19 |
| 11735525 | Power delivery network for CFET with buried power rails | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2023-08-22 |
| 11721582 | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits | Mark I. Gardner, H. Jim Fulford | 2023-08-08 |
| 11721551 | Localized stress regions for three-dimension chiplet formation | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford | 2023-08-08 |
| 11694957 | Programmable connection segment and method of forming the same | Mark I. Gardner, H. Jim Fulford | 2023-07-04 |
| 11688642 | Localized stress regions for three-dimension chiplet formation | Daniel Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford | 2023-06-27 |
| 11682559 | Method to form narrow slot contacts | Michael Murphy, Jodi Grzeskowiak | 2023-06-20 |
| 11676968 | Coaxial contacts for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Kandabara Tapily | 2023-06-13 |
| 11640937 | Horizontal programmable conducting bridges between conductive lines | H. Jim Fulford, Mark I. Gardner | 2023-05-02 |
| 11640118 | Method of pattern alignment for field stitching | — | 2023-05-02 |
| 11631671 | 3D complementary metal oxide semiconductor (CMOS) device and method of forming the same | H. Jim Fulford, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann +1 more | 2023-04-18 |
| 11630397 | Method for producing overlay results with absolute reference for semiconductor manufacturing | — | 2023-04-18 |
| 11616053 | Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device | Jeffrey Smith, Kandabara Tapily | 2023-03-28 |
| 11616020 | Power distribution network for 3D logic and memory | Lars Liebmann, Jeffrey Smith, Kandabara Tapily | 2023-03-28 |
| 11574845 | Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices | Daniel Chanemougame, Lars Liebmann, Jeffrey Smith | 2023-02-07 |
| 11526088 | Coaxial see-through alignment imaging system | Anthony R. Schepis, David Conklin | 2022-12-13 |
| 11513445 | Tunable wavelength see-through layer stack | — | 2022-11-29 |
| 11495540 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Lars Liebmann, Jeffrey Smith | 2022-11-08 |
| 11488947 | Highly regular logic design for efficient 3D integration | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2022-11-01 |
| 11484993 | Substrate holding apparatus and method for shape metrology | Hoyoung Kang | 2022-11-01 |
| 11460775 | Method and system for prevention of metal contamination by using a self-assembled monolayer coating | Hoyoung Kang, Corey Lemley | 2022-10-04 |
| 11450671 | Semiconductor apparatus having stacked devices and method of manufacture thereof | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2022-09-20 |
| 11443953 | Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning | Kandabara Tapily, Gerrit J. Leusink | 2022-09-13 |
| 11444082 | Semiconductor apparatus having stacked gates and method of manufacture thereof | Jeffrey Smith, Kandabara Tapily, Subhadeep Kal, Gerrit J. Leusink | 2022-09-13 |
| 11437376 | Compact 3D stacked-CFET architecture for complex logic cells | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2022-09-06 |