Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12414367 | Tapered device for lateral gate all around devices | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2025-09-09 |
| 12336274 | Self-aligned method for vertical recess for 3D device integration | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Subhadeep Kal, Kandabara Tapily +1 more | 2025-06-17 |
| 12224281 | Interdigitated device stack | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Brian Tracy Cline, Xiaoqing Xu +1 more | 2025-02-11 |
| 12218135 | Wiring in diffusion breaks in an integrated circuit | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2025-02-04 |
| 12176293 | Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Brian Tracy Cline, Xiaoqing Xu +1 more | 2024-12-24 |
| 12051638 | Integrated high efficiency transistor cooling | Daniel Chanemougame, Lars Liebmann, Jeffrey Smith | 2024-07-30 |
| 12002862 | Inter-level handshake for dense 3D logic integration | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2024-06-04 |
| 11961802 | Power-tap pass-through to connect a buried power rail to front-side power distribution network | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2024-04-16 |
| 11923364 | Double cross-couple for two-row flip-flop using CFET | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2024-03-05 |
| 11830852 | Multi-tier backside power delivery network for dense gate-on-gate 3D logic | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Brian Tracy Cline, Xiaoqing Xu +1 more | 2023-11-28 |
| 11764266 | Three-dimensional semiconductor device | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2023-09-19 |
| 11764113 | Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds | Jeffrey Smith, Daniel Chanemougame, Lars Liebmann, Robert D. Clark, Anton J. deVilliers | 2023-09-19 |
| 11723187 | Three-dimensional memory cell structure | Lars Liebmann, Daniel Chanemougame | 2023-08-08 |
| 11581242 | Integrated high efficiency gate on gate cooling | Daniel Chanemougame, Lars Liebmann, Jeffrey Smith | 2023-02-14 |
| 11532708 | Stacked three-dimensional field-effect transistors | Lars Liebmann, Jeffrey Smith, Daniel Chanemougame | 2022-12-20 |
| 6829755 | Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis | Peter J. Osler | 2004-12-07 |
| 6671218 | System and method for hiding refresh cycles in a dynamic type content addressable memory | Jonathan B. Ashbrook, Michael Bogaczyk, Albert M. Chu, Ezra D. B. Hall, Daryl M. Seitzer | 2003-12-30 |
| 6588000 | Method of partitioning large transistor design to facilitate transistor level timing | Peter J. Osler | 2003-07-01 |
| 6532520 | Method and apparatus for allocating data and instructions within a shared cache | Alvar A. Dean, Marc R. Faucher, John W. Goetz, Kenneth J. Goodnow, Stephen W. Mahin +1 more | 2003-03-11 |
| 6449693 | Method and apparatus for improving caching within a processor system | John W. Goetz, Stephen W. Mahin, Wilbur D. Pricer | 2002-09-10 |
| 6178467 | Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode | Marc R. Faucher | 2001-01-23 |
| 5796621 | Circuit delay abstraction tool | Peter E. Dudley, Gara Pruesse | 1998-08-18 |
| 5239481 | Method for measuring pulse distortion | Thomas W. Brooks, Caryn G. Melrose, Frank Albert Nemec, II, James J. Tomczak | 1993-08-24 |