XX

Xiaoqing Xu

NV NVIDIA: 11 patents #639 of 7,811Top 9%
TL Tokyo Electron Limited: 3 patents #2,069 of 5,567Top 40%
SS Societe Des Produits Nestle S.A.: 1 patents #653 of 1,324Top 50%
UM United Microelectronics: 1 patents #2,686 of 4,560Top 60%
Overall (All Time): #187,938 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12224281 Interdigitated device stack Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline +1 more 2025-02-11
12214239 Dumbbell, barbell, and kettlebell Zhaohong Yu 2025-02-04
12176293 Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline +1 more 2024-12-24
D1048700 Thread spool 2024-10-29
12045271 Methods and systems for facilitating the creation of food and/or beverage product concepts Seyed Reza Hosseini Kouh Kamari, Rafael Pinto Peixoto, Stéphanie Mehlinger, Amanda Makhpal Talhat 2024-07-23
11959950 Method and apparatus for power measurement in electronic circuit design and analysis Zhiyao Xie, Shidhartha Das, Matthew James Walker, Kumara Guru Palaniswamy, Matthew Paul Elwood 2024-04-16
11830852 Multi-tier backside power delivery network for dense gate-on-gate 3D logic Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline +1 more 2023-11-28
11726116 Method and apparatus for on-chip power metering using automated selection of signal power proxies Zhiyao Xie, Shidhartha Das 2023-08-15
11650341 Method and system for analyzing seismic active field based on expansion of empirical orthogonal function Heqing Ma, Mingzhi Yang, Guofu Luo, Xiaojun Ma, Xianwei Zeng +3 more 2023-05-16
11569219 TSV coupled integrated circuits and methods Rahul Mathur, Andy Wangkun Chen, Mudit Bhargava, Brian Tracy Cline, Saurabh Sinha 2023-01-31
D973977 Pet harness 2022-12-27
D973978 Pet harness 2022-12-27
11455454 Methods and apparatuses for concurrent coupling of inter-tier connections Chien-Ju Chao, Pranavi Chandupatla, Saurabh Sinha, Sheng-En Hung 2022-09-27
11295053 Dielet design techniques Brian Tracy Cline, Saurabh Sinha, Stephen Lewis Moore, Mudit Bhargava 2022-04-05
11228316 Method, system and circuit for multi-die timing signal distribution Saurabh Sinha, Sheng-En Hung, Chien-Ju Chao 2022-01-18
D939823 Pet bag 2022-01-04
11120191 Multi-tier co-placement for integrated circuitry Brian Tracy Cline, Stephen Lewis Moore, Saurabh Sinha 2021-09-14
10825745 Multi-die integrated circuits with improved testability Saurabh Sinha, Joel Thornton Irby, Mudit Bhargava 2020-11-03
10796053 Computer implemented system and method for generating a layout of a cell defining a circuit component Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Brian Tracy Cline, Andy Wangkun Chen +6 more 2020-10-06
10599806 Multi-tier co-placement for integrated circuitry Brian Tracy Cline, Stephen Lewis Moore, Saurabh Sinha 2020-03-24
10083269 Computer implemented system and method for generating a layout of a cell defining a circuit component Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Brian Lee, Brian Tracy Cline +12 more 2018-09-25
9305887 Seal ring structure with a v-shaped dielectric layer conformally overlapping a conductive layer Fan Zeng, Ching Hwa Tey 2016-04-05