Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
BC

Brian Tracy Cline — 33 Patents

NVIDIA: 30 patents #173 of 7,811Top 3%
TLTokyo Electron Limited: 3 patents #2,069 of 5,567Top 40%
University of Michigan: 1 patents #1,906 of 4,352Top 45%
Austin, TX: #894 of 18,064 inventorsTop 5%
Texas: #3,395 of 125,132 inventorsTop 3%
Overall (All Time): #105,480 of 4,157,543Top 3%
33 Patents All Time
Brian Tracy Cline has been granted 33 US patents while listed as an inventor at NVIDIA. The first was granted in 2014 and the most recent in August 2025. Brian Tracy Cline ranks #105,480 of 4,157,543 US inventors in our database (top 2.5%). Patent records list Brian Tracy Cline in Austin, TX, US.

Patents per Year

Patents granted per year, 2014 to 2025Bar chart with a peak of 9 patents in 2020.peak 92014: 1 patents20142016: 1 patents2017: 2 patents20172018: 5 patents2019: 2 patents20192020: 9 patents2021: 4 patents20212022: 1 patents2023: 3 patents20232024: 3 patents2025: 2 patents2025

Issued Patents All Time

Showing 1–25 of 33 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12392959 Optical waveguide connecting device Vinay Vashishtha, Mudit Bhargava, Saurabh Sinha, Gregory Munson Yeric 2025-08-19
12224281 Interdigitated device stack Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Xiaoqing Xu +1 more 2025-02-11
12176293 Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Xiaoqing Xu +1 more 2024-12-24
12170130 Systems, devices, and/or processes for OMIC and/or behavioral content processing Renee Marie St Amant, Peter James Samuel Ferguson, Gary Dale Carpenter 2024-12-17 $358,585,000
11895816 Bitcell architecture Amit Chhabra 2024-02-06 $55,058,000
11830852 Multi-tier backside power delivery network for dense gate-on-gate 3D logic Lars Liebmann, Jeffrey Smith, Daniel Chanemougame, Paul Gutwin, Xiaoqing Xu +1 more 2023-11-28
11625522 Method and apparatus for generating three-dimensional integrated circuit design Saurabh Sinha, Kyungwook Chang, Ebbin R. Southerland, Jr. 2023-04-11
11569219 TSV coupled integrated circuits and methods Rahul Mathur, Xiaoqing Xu, Andy Wangkun Chen, Mudit Bhargava, Saurabh Sinha 2023-01-31
11295053 Dielet design techniques Xiaoqing Xu, Saurabh Sinha, Stephen Lewis Moore, Mudit Bhargava 2022-04-05
11126778 Wirelength distribution schemes and techniques Divya Madapusi Srinivas Prasad, Saurabh Sinha, Stephen Lewis Moore 2021-09-21
11120191 Multi-tier co-placement for integrated circuitry Xiaoqing Xu, Stephen Lewis Moore, Saurabh Sinha 2021-09-14
11004479 Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array Mudit Bhargava, Shidhartha Das, George McNeil Lattimore 2021-05-11
10922608 Spiking neural network Naveen Suda, Vikas Chandra, Saurabh Sinha, Shidhartha Das 2021-02-16
10841299 Systems, devices, and/or processes for omic content processing and/or partitioning Renee Marie St Amant, Peter James Samuel Ferguson, Gary Dale Carpenter 2020-11-17
10841083 Systems, devices, and/or processes for OMIC content processing and/or communication Renee Marie St Amant, Peter James Samuel Ferguson, Gary Dale Carpenter 2020-11-17
10796053 Computer implemented system and method for generating a layout of a cell defining a circuit component Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Xiaoqing Xu, Andy Wangkun Chen +6 more 2020-10-06
10741246 Method, system and device for integration of volatile and non-volatile memory bitcells Mudit Bhargava, George McNeil Lattimore, Bal S. Sandhu 2020-08-11
10678985 Method for generating three-dimensional integrated circuit design Saurabh Sinha, Kyungwook Chang, Ebbin R. Southerland, Jr. 2020-06-09
10657218 Wirelength distribution schemes and techniques Divya Madapusi Srinivas Prasad, Saurabh Sinha, Stephen Lewis Moore 2020-05-19
10641953 Optical waveguide connecting device Vinay Vashishtha, Mudit Bhargava, Saurabh Sinha, Gregory Munson Yeric 2020-05-05
10607659 Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array Mudit Bhargava, Shidhartha Das, George McNeil Lattimore 2020-03-31
10599806 Multi-tier co-placement for integrated circuitry Xiaoqing Xu, Stephen Lewis Moore, Saurabh Sinha 2020-03-24
10381076 Circuit and method for configurable impedance array Azeez Bhavnagarwala, Vikas Chandra 2019-08-13
10366753 Correlated electron switch programmable fabric Lucian Shifren, Greg Yeric, Saurabh Sinha, Vikas Chandra 2019-07-30
10083269 Computer implemented system and method for generating a layout of a cell defining a circuit component Paul Christopher de Dood, Marlin Wayne Frederick, Jr., Jerry C. Wang, Brian Lee, Xiaoqing Xu +12 more 2018-09-25