Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11625522 | Method and apparatus for generating three-dimensional integrated circuit design | Saurabh Sinha, Brian Tracy Cline, Ebbin R. Southerland, Jr. | 2023-04-11 |
| 10678985 | Method for generating three-dimensional integrated circuit design | Saurabh Sinha, Brian Tracy Cline, Ebbin R. Southerland, Jr. | 2020-06-09 |
| 9929149 | Using inter-tier vias in integrated circuits | Saurabh Sinha, Robert Campbell Aitken, Brian Tracy Cline, Gregory Munson Yeric | 2018-03-27 |