Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248743 | Cell architecture with backside power rails | Sharath Koodali Edathil | 2025-03-11 |
| 11836432 | Cell architecture with backside power rails | Sharath Koodali Edathil | 2023-12-05 |
| 11380618 | Power distribution circuitry | Karen Lee Delk | 2022-07-05 |
| 11288432 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Gus Yeung, Sriram Thyagarajan | 2022-03-29 |
| 11152139 | Power rail stitching technique | Karen Lee Delk, Sharrone Rena Smith | 2021-10-19 |
| 11068639 | Metal layout techniques | Ettore Amirante, Ronald Paxton Preston, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong | 2021-07-20 |
| 11011222 | Memory structure with bitline strapping | Ronald Paxton Preston, Andy Wangkun Chen, Yew Keong Chong | 2021-05-18 |
| 10923425 | Power distribution | Karen Lee Delk | 2021-02-16 |
| 10796053 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Paul Christopher de Dood, Jerry C. Wang, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen +6 more | 2020-10-06 |
| 10417371 | Power grid healing techniques | Karen Lee Delk, Ravindra Narayana Rao | 2019-09-17 |
| 10210303 | Sleep signal stitching technique | Ravindra Narayana Rao, Karen Lee Delk, Stefan Charles Creaser | 2019-02-19 |
| 10204894 | Via placement within an integrated circuit | — | 2019-02-12 |
| 10083269 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Paul Christopher de Dood, Jerry C. Wang, Brian Lee, Brian Tracy Cline, Xiaoqing Xu +12 more | 2018-09-25 |
| 10083833 | Integration fill technique | Ronald Paxton Preston | 2018-09-25 |
| 9892220 | Method and apparatus for adjusting a timing derate for static timing analysis | Karen Lee Delk, Lena Ahlen, James Dennis Dodrill | 2018-02-13 |
| 9871039 | Resistance mitigation in physical design | Jean-Luc Pelloie | 2018-01-16 |
| 9690889 | Method for adjusting a timing derate for static timing analysis | Karen Lee Delk, Lena Ahlen, James Dennis Dodrill | 2017-06-27 |
| 9653413 | Power grid conductor placement within an integrated circuit | Karen Lee Delk | 2017-05-16 |
| 9454633 | Via placement within an integrated circuit | — | 2016-09-27 |
| 9450571 | Data and clock signal voltages within an integrated circuit | Ashwani Kumar Srivastava | 2016-09-20 |
| 8959472 | Considering compatibility of adjacent boundary regions for standard cells placement and routing | Jean-Luc Pelloie | 2015-02-17 |
| 8824215 | Data storage circuit that retains state during precharge | Akhtar ALAM, Sumana Pal | 2014-09-02 |
| 8645893 | Method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance | Gus Yeung, Martin Jay Kinkade | 2014-02-04 |
| 8456140 | Power control apparatus and method for controlling a supply voltage for an associated circuit | Sanjay Bhagwan Patil, Valentina Gomez | 2013-06-04 |
| 8456214 | State retention circuit and method of operation of such a circuit | — | 2013-06-04 |