Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11586445 | Modular gated multiplier circuitry and multiplication technique | Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, Yew Keong Chong | 2023-02-21 |
| 11520658 | Non-volatile memory on chip | Joel Thornton Irby, Wendy Arnott Elsasser, Mudit Bhargava, Yew Keong Chong, George McNeil Lattimore | 2022-12-06 |
| 10641822 | Critical path architect | Satheesh Balasubramanian, Shardendu Shekhar, Sainarayanan Karatholuvu Suryanarayanan | 2020-05-05 |
| 10187063 | Sequential logic device with single-phase clock operation | Amanda Ashley Scantlin, Anil Kumar Baratam, Susan M. Graham | 2019-01-22 |
| 10020031 | Location-based optimization for memory systems | Yew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan, Gus Yeung | 2018-07-10 |
| 9912338 | Apparatus and method for reduced latency signal synchronization | Paul Christopher de Dood | 2018-03-06 |
| 9892220 | Method and apparatus for adjusting a timing derate for static timing analysis | Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen | 2018-02-13 |
| 9823298 | Critical path architect | Satheesh Balasubramanian, Shardendu Shekhar, Sainarayanan Karatholuvu Suryanarayanan | 2017-11-21 |
| 9825636 | Apparatus and method for reduced latency signal synchronization | Amanda Ashley Scantlin | 2017-11-21 |
| 9690889 | Method for adjusting a timing derate for static timing analysis | Marlin Wayne Frederick, Jr., Karen Lee Delk, Lena Ahlen | 2017-06-27 |
| 9651620 | Measurements circuitry and method for generating an oscillating output signal used to derive timing information | Ramesh Manohar | 2017-05-16 |
| 9479147 | Synchroniser flip-flop | Satheesh Balasubramanian | 2016-10-25 |
| 8024591 | Method of and apparatus for reducing power consumption within an integrated circuit | Lars Soendergaard Bertelsen, Michael Allen, Joern Soerensen, Joseph Patrick Geisler | 2011-09-20 |