Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11520658 | Non-volatile memory on chip | Joel Thornton Irby, Mudit Bhargava, Yew Keong Chong, George McNeil Lattimore, James Dennis Dodrill | 2022-12-06 |
| 11137919 | Initialisation of a storage device | Wei Wang, Stephan Diestelhorst | 2021-10-05 |
| 10866899 | Method and apparatus for control of a tiered memory system | Prakash S. Ramrakhyani, Joshua Randall | 2020-12-15 |
| 10860495 | Storage circuitry responsive to a tag-matching command | Andreas Hansson, Nikos NIKOLERIS | 2020-12-08 |
| 10831678 | Multi-tier cache placement mechanism | Jiajun Wang, Prakash S. Ramrakhyani, Wei Wang | 2020-11-10 |
| 10795815 | Method and apparatus for maintaining data coherence in a non-uniform compute device | Jonathan Curtis Beard, Stephan Diestelhorst | 2020-10-06 |
| 10733313 | Counter integrity tree for memory security | Prakash S. Ramrakhyani, Roberto Avanzi | 2020-08-04 |
| 10642743 | Apparatus and method of handling caching of persistent data | Wei Wang, Stephan Diestelhorst, Andreas Lars Sandberg, Nikos NIKOLERIS | 2020-05-05 |
| 10552152 | Method and apparatus for scheduling in a non-uniform compute device | Jonathan Curtis Beard, Eric Van Hensbergen, Stephan Diestelhorst | 2020-02-04 |
| 10540297 | Memory organization for security and reliability | Gururaj Saileshwar, Prakash S. Ramrakhyani | 2020-01-21 |
| 10445094 | Method and apparatus for reordering in a non-uniform compute device | Jonathan Curtis Beard, Shibo Wang | 2019-10-15 |
| 10417141 | Method and apparatus for hardware management of multiple memory pools | Andrea Pellegrini, Kshitij Sudan, Ali Ghassan Saidi | 2019-09-17 |
| 10339050 | Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands | Andreas Hansson, Michael Andrew Campbell | 2019-07-02 |
| 9280454 | Method and system for re-ordering bits in a memory system | Marc A. Greenberg | 2016-03-08 |