Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Vikas Chandra — 54 Patents

NVIDIA: 35 patents #135 of 7,811Top 2%
IBM: 7 patents #14,688 of 70,183Top 25%
Meta: 5 patents #1,437 of 6,845Top 25%
NENetiq: 3 patents #15 of 74Top 25%
TATabula: 2 patents #16 of 42Top 40%
Mastercard: 1 patents #1,122 of 2,005Top 60%
San Jose, CA: #847 of 32,062 inventorsTop 3%
California: #7,050 of 386,348 inventorsTop 2%
Overall (All Time): #46,969 of 4,157,543Top 2%
54 Patents All Time
Vikas Chandra has been granted 54 US patents while listed as an inventor at NVIDIA. The first was granted in 2002 and the most recent in December 2025. Vikas Chandra ranks #46,969 of 4,157,543 US inventors in our database (top 1.1%). Patent records list Vikas Chandra in San Jose, CA, US.

Issued Patents All Time

Showing 1–25 of 54 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12488481 Video reconstruction from videos with ultra-low frame-per-second Xiaoyu Xiang, Ingrid A. Cotoros, Rakesh Ranjan 2025-12-02
11972349 Flexible compute array utilization in a tensor processor Liangzhen Lai, Yu-Hsin Chen 2024-04-30 $1,258,665,000
11954580 Spatial tiling of compute arrays with shared control Harshit Khaitan, Ganesh Venkatesh 2024-04-09 $740,025,000
11698529 Systems and methods for distributing a neural network across multiple computing devices Liangzhen Lai, Pierce I-Jen Chuang, Ganesh Venkatesh 2023-07-11 $594,919,000
11494776 Method and system for providing performance assessment of terminal devices Balamurali Balasubramanian, Amresh M D 2022-11-08 $271,156,000
11355192 CES-based latching circuits Robert Campbell Aitken, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs +2 more 2022-06-07
11042466 Exception prediction before an actual exception during debugging Sarika Sinha 2021-06-22 $6,016,000
10977002 System and method for supporting alternate number format for efficient multiplication Ganesh Venkatesh, Liangzhen Lai, Pierce I-Jen Chuang, Meng Li 2021-04-13 $167,872,000
10922608 Spiking neural network Naveen Suda, Brian Tracy Cline, Saurabh Sinha, Shidhartha Das 2021-02-16
10761976 Method and apparatus for memory wear leveling Mudit Bhargava, Joel Thornton Irby 2020-09-01
10438022 Logic encryption using on-chip memory cells Mudit Bhargava 2019-10-08
10381076 Circuit and method for configurable impedance array Azeez Bhavnagarwala, Brian Tracy Cline 2019-08-13
10366753 Correlated electron switch programmable fabric Lucian Shifren, Greg Yeric, Saurabh Sinha, Brian Tracy Cline 2019-07-30
10267831 Process variation compensation with correlated electron switch devices Mudit Bhargava 2019-04-23
10236888 Correlated electron switch device Robert Campbell Aitken 2019-03-19
10216609 Exception prediction before an actual exception during debugging Sarika Sinha 2019-02-26 $2,499,000
10169194 Multi-thread sequencing Srinivasan S. Muthuswamy, Sarika Sinha 2019-01-01
10122384 Logical interleaver Liangzhen Lai, Gary Dale Carpenter 2018-11-06
10115473 Method, system and device for correlated electron switch (CES) device operation Mudit Bhargava 2018-10-30
10056143 Correlated electron switch programmable fabric Lucian Shifren, Greg Yeric, Saurabh Sinha, Brian Tracy Cline 2018-08-21
10036774 Integrated circuit device comprising environment-hardened die and less-environment-hardened die Gregory Munson Yeric 2018-07-31
10032487 One-time and multi-time programming using a correlated electron switch Lucian Shifren, Robert Campbell Aitken, Bal S. Sandhu 2018-07-24
9922152 Computer implemented system and method for reducing failure in time soft errors of a circuit design Liangzhen Lai 2018-03-20
9905295 Circuit and method for configurable impedance array Azeez Bhavnagarwala, Brian Tracy Cline 2018-02-27
9891976 Error detection circuitry for use with memory Andy Wangkun Chen, Mudit Bhargava, Paul Gilbert Meyer 2018-02-13